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[2001:8b0:1d0::1]) by mx.google.com with ESMTPS id kn7si21650602bkb.11.2013.12.03.13.52.33 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Tue, 03 Dec 2013 13:52:34 -0800 (PST) Received-SPF: neutral (google.com: 2001:8b0:1d0::1 is neither permitted nor denied by best guess record for domain of pm215@archaic.org.uk) client-ip=2001:8b0:1d0::1; Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1VnxsD-0006J0-Kh; Tue, 03 Dec 2013 21:51:17 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Alexander Graf , C Fontana , Dirk Mueller , Michael Matz , Laurent Desnogues , Richard Henderson , kvmarm@lists.cs.columbia.edu Subject: [PATCH 12/12] target-arm: A64: add support for compare and branch imm Date: Tue, 3 Dec 2013 21:51:17 +0000 Message-Id: <1386107477-24165-13-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1386107477-24165-1-git-send-email-peter.maydell@linaro.org> References: <1386107477-24165-1-git-send-email-peter.maydell@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: peter.maydell@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.128.177 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Alexander Graf This patch adds emulation for the compare and branch insns, CBZ and CBNZ. Signed-off-by: Alexander Graf [claudio: adapted to new decoder, compare with immediate 0, introduce read_cpu_reg to get the 0 extension on (!sf)] Signed-off-by: Claudio Fontana Signed-off-by: Peter Maydell --- target-arm/translate-a64.c | 45 ++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 43 insertions(+), 2 deletions(-) diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index bcb59db..37dc462 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -184,6 +184,18 @@ static TCGv_i64 cpu_reg(DisasContext *s, int reg) } } +/* read a cpu register in 32bit/64bit mode to dst */ +static void read_cpu_reg(DisasContext *s, TCGv_i64 dst, int reg, int sf) +{ + if (reg == 31) { + tcg_gen_movi_i64(dst, 0); + } else if (sf) { + tcg_gen_mov_i64(dst, cpu_X[reg]); + } else { /* (!sf) */ + tcg_gen_ext32u_i64(dst, cpu_X[reg]); + } +} + /* * the instruction disassembly implemented here matches * the instruction encoding classifications in chapter 3 (C3) @@ -209,10 +221,39 @@ static void disas_uncond_b_imm(DisasContext *s, uint32_t insn) gen_goto_tb(s, 0, addr); } -/* Compare & branch (immediate) */ +/* C3.2.1 Compare & branch (immediate) + * 31 30 25 24 23 5 4 0 + * +----+-------------+----+---------------------+--------+ + * | sf | 0 1 1 0 1 0 | op | imm19 | Rt | + * +----+-------------+----+---------------------+--------+ + */ static void disas_comp_b_imm(DisasContext *s, uint32_t insn) { - unsupported_encoding(s, insn); + unsigned int sf, op, rt; + uint64_t addr; + int label_nomatch; + TCGv_i64 tcg_cmp; + + sf = extract32(insn, 31, 1); + op = extract32(insn, 24, 1); + rt = extract32(insn, 0, 5); + addr = s->pc + sextract32(insn, 5, 19) * 4 - 4; + + tcg_cmp = tcg_temp_new_i64(); + read_cpu_reg(s, tcg_cmp, rt, sf); + label_nomatch = gen_new_label(); + + if (op) { /* CBNZ */ + tcg_gen_brcondi_i64(TCG_COND_EQ, tcg_cmp, 0, label_nomatch); + } else { /* CBZ */ + tcg_gen_brcondi_i64(TCG_COND_NE, tcg_cmp, 0, label_nomatch); + } + + tcg_temp_free_i64(tcg_cmp); + + gen_goto_tb(s, 0, addr); + gen_set_label(label_nomatch); + gen_goto_tb(s, 1, s->pc); } /* C3.2.5 Test & branch (immediate)