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[2001:8b0:1d0::1]) by mx.google.com with ESMTPS id i3si31671050wja.170.2013.12.03.13.52.31 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Tue, 03 Dec 2013 13:52:31 -0800 (PST) Received-SPF: neutral (google.com: 2001:8b0:1d0::1 is neither permitted nor denied by best guess record for domain of pm215@archaic.org.uk) client-ip=2001:8b0:1d0::1; Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1VnxsD-0006Is-I2; Tue, 03 Dec 2013 21:51:17 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Alexander Graf , C Fontana , Dirk Mueller , Michael Matz , Laurent Desnogues , Richard Henderson , kvmarm@lists.cs.columbia.edu Subject: [PATCH 10/12] target-arm: A64: add support for conditional branches Date: Tue, 3 Dec 2013 21:51:15 +0000 Message-Id: <1386107477-24165-11-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1386107477-24165-1-git-send-email-peter.maydell@linaro.org> References: <1386107477-24165-1-git-send-email-peter.maydell@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: peter.maydell@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.128.176 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Alexander Graf This patch adds emulation for the conditional branch (b.cond) instruction. Signed-off-by: Alexander Graf [claudio: adapted to new decoder structure, reused arm infrastructure for checking the flags] Signed-off-by: Claudio Fontana Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target-arm/translate-a64.c | 29 +++++++++++++++++++++++++++-- target-arm/translate.c | 14 +++++++++----- target-arm/translate.h | 2 ++ 3 files changed, 38 insertions(+), 7 deletions(-) diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index 48281ff..3c0748d 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -221,10 +221,35 @@ static void disas_test_b_imm(DisasContext *s, uint32_t insn) unsupported_encoding(s, insn); } -/* Conditional branch (immediate) */ +/* C3.2.2 / C5.6.19 Conditional branch (immediate) + * 31 25 24 23 5 4 3 0 + * +---------------+----+---------------------+----+------+ + * | 0 1 0 1 0 1 0 | o1 | imm19 | o0 | cond | + * +---------------+----+---------------------+----+------+ + */ static void disas_cond_b_imm(DisasContext *s, uint32_t insn) { - unsupported_encoding(s, insn); + unsigned int cond; + uint64_t addr; + + if ((insn & (1 << 4)) || (insn & (1 << 24))) { + unallocated_encoding(s); + return; + } + addr = s->pc + sextract32(insn, 5, 19) * 4 - 4; + cond = extract32(insn, 0, 4); + + if (cond < 0x0e) { + /* genuinely conditional branches */ + int label_nomatch = gen_new_label(); + arm_gen_test_cc(cond ^ 1, label_nomatch); + gen_goto_tb(s, 0, addr); + gen_set_label(label_nomatch); + gen_goto_tb(s, 1, s->pc); + } else { + /* 0xe and 0xf are both "always" conditions */ + gen_goto_tb(s, 0, addr); + } } /* C5.6.68 HINT */ diff --git a/target-arm/translate.c b/target-arm/translate.c index 553bded..9e2d1eb 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -671,7 +671,11 @@ static void gen_thumb2_parallel_addsub(int op1, int op2, TCGv_i32 a, TCGv_i32 b) } #undef PAS_OP -static void gen_test_cc(int cc, int label) +/* + * generate a conditional branch based on ARM condition code cc. + * This is common between ARM and Aarch64 targets. + */ +void arm_gen_test_cc(int cc, int label) { TCGv_i32 tmp; int inv; @@ -6903,7 +6907,7 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s) /* if not always execute, we generate a conditional jump to next instruction */ s->condlabel = gen_new_label(); - gen_test_cc(cond ^ 1, s->condlabel); + arm_gen_test_cc(cond ^ 1, s->condlabel); s->condjmp = 1; } if ((insn & 0x0f900000) == 0x03000000) { @@ -8910,7 +8914,7 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw op = (insn >> 22) & 0xf; /* Generate a conditional jump to next instruction. */ s->condlabel = gen_new_label(); - gen_test_cc(op ^ 1, s->condlabel); + arm_gen_test_cc(op ^ 1, s->condlabel); s->condjmp = 1; /* offset[11:1] = insn[10:0] */ @@ -9267,7 +9271,7 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s) cond = s->condexec_cond; if (cond != 0x0e) { /* Skip conditional when condition is AL. */ s->condlabel = gen_new_label(); - gen_test_cc(cond ^ 1, s->condlabel); + arm_gen_test_cc(cond ^ 1, s->condlabel); s->condjmp = 1; } } @@ -9940,7 +9944,7 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s) } /* generate a conditional jump to next instruction */ s->condlabel = gen_new_label(); - gen_test_cc(cond ^ 1, s->condlabel); + arm_gen_test_cc(cond ^ 1, s->condlabel); s->condjmp = 1; /* jump to the offset */ diff --git a/target-arm/translate.h b/target-arm/translate.h index 23a45da..a6f6b3e 100644 --- a/target-arm/translate.h +++ b/target-arm/translate.h @@ -65,4 +65,6 @@ static inline void gen_a64_set_pc_im(uint64_t val) } #endif +void arm_gen_test_cc(int cc, int label); + #endif /* TARGET_ARM_TRANSLATE_H */