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[2001:8b0:1d0::1]) by mx.google.com with ESMTPS id cr8si2917723wib.0.2013.11.22.09.17.29 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Fri, 22 Nov 2013 09:17:29 -0800 (PST) Received-SPF: neutral (google.com: 2001:8b0:1d0::1 is neither permitted nor denied by best guess record for domain of pm215@archaic.org.uk) client-ip=2001:8b0:1d0::1; Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1VjuM3-0002jU-6O; Fri, 22 Nov 2013 17:17:19 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, kvmarm@lists.cs.columbia.edu Subject: [PATCH v9 09/11] target-arm: Don't hardcode KVM target CPU to be A15 Date: Fri, 22 Nov 2013 17:17:16 +0000 Message-Id: <1385140638-10444-10-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1385140638-10444-1-git-send-email-peter.maydell@linaro.org> References: <1385140638-10444-1-git-send-email-peter.maydell@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: peter.maydell@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.212.49 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Instead of assuming that a KVM target CPU must always be a Cortex-A15 and hardcoding this in kvm_arch_init_vcpu(), store the KVM_ARM_TARGET_* value in the ARMCPU class, and use that. Signed-off-by: Peter Maydell --- target-arm/cpu-qom.h | 5 +++++ target-arm/cpu.c | 2 ++ target-arm/kvm-consts.h | 11 +++++++++++ target-arm/kvm.c | 7 ++++++- 4 files changed, 24 insertions(+), 1 deletion(-) diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h index 8bd3e36..f32178a 100644 --- a/target-arm/cpu-qom.h +++ b/target-arm/cpu-qom.h @@ -97,6 +97,11 @@ typedef struct ARMCPU { /* Should CPU start in PSCI powered-off state? */ bool start_powered_off; + /* [QEMU_]KVM_ARM_TARGET_* constant for this CPU, or + * QEMU_KVM_ARM_TARGET_NONE if the kernel doesn't support this CPU type. + */ + uint32_t kvm_target; + /* The instance init functions for implementation-specific subclasses * set these fields to specify the implementation-dependent values of * various constant registers and reset values of non-constant diff --git a/target-arm/cpu.c b/target-arm/cpu.c index 0325815..0635e78 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -223,6 +223,7 @@ static void arm_cpu_initfn(Object *obj) * picky DTB consumer will also provide a helpful error message. */ cpu->dtb_compatible = "qemu,unknown"; + cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; if (tcg_enabled() && !inited) { inited = true; @@ -685,6 +686,7 @@ static void cortex_a15_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); set_feature(&cpu->env, ARM_FEATURE_LPAE); + cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15; cpu->midr = 0x412fc0f1; cpu->reset_fpsid = 0x410430f0; cpu->mvfr0 = 0x10110222; diff --git a/target-arm/kvm-consts.h b/target-arm/kvm-consts.h index 4062f11..2bba0bd 100644 --- a/target-arm/kvm-consts.h +++ b/target-arm/kvm-consts.h @@ -48,6 +48,17 @@ MISMATCH_CHECK(PSCI_FN_CPU_OFF, KVM_PSCI_FN_CPU_OFF) MISMATCH_CHECK(PSCI_FN_CPU_ON, KVM_PSCI_FN_CPU_ON) MISMATCH_CHECK(PSCI_FN_MIGRATE, KVM_PSCI_FN_MIGRATE) +#define QEMU_KVM_ARM_TARGET_CORTEX_A15 0 + +/* There's no kernel define for this: sentinel value which + * matches no KVM target value for either 64 or 32 bit + */ +#define QEMU_KVM_ARM_TARGET_NONE UINT_MAX + +#ifndef TARGET_AARCH64 +MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_CORTEX_A15, KVM_ARM_TARGET_CORTEX_A15) +#endif + #undef MISMATCH_CHECK #endif diff --git a/target-arm/kvm.c b/target-arm/kvm.c index 80c58c5..182db85 100644 --- a/target-arm/kvm.c +++ b/target-arm/kvm.c @@ -77,7 +77,12 @@ int kvm_arch_init_vcpu(CPUState *cs) struct kvm_reg_list *rlp; ARMCPU *cpu = ARM_CPU(cs); - init.target = KVM_ARM_TARGET_CORTEX_A15; + if (cpu->kvm_target == QEMU_KVM_ARM_TARGET_NONE) { + fprintf(stderr, "KVM is not supported for this guest CPU type\n"); + return -EINVAL; + } + + init.target = cpu->kvm_target; memset(init.features, 0, sizeof(init.features)); if (cpu->start_powered_off) { init.features[0] = 1 << KVM_ARM_VCPU_POWER_OFF;