From patchwork Thu Sep 5 14:38:28 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 19772 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-vb0-f71.google.com (mail-vb0-f71.google.com [209.85.212.71]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id D0A4924692 for ; Thu, 5 Sep 2013 14:38:32 +0000 (UTC) Received: by mail-vb0-f71.google.com with SMTP id g17sf2018842vbg.2 for ; Thu, 05 Sep 2013 07:38:32 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=mime-version:x-gm-message-state:delivered-to:from:to:cc:subject :date:message-id:in-reply-to:references:sender:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :list-post:list-help:list-archive:list-unsubscribe; bh=szY6RwZSMIPdyNnx80QMcTl59EzLhNqM0ckdJc4ozik=; b=N3zp5tHeOM5GRRzKBbNjt9ZNFzexvL8gYmP6sNhVxYnJK9L9Nr3+MT67vRgl969Dmm h0P2MC5qpUunosP8/DgXKT3tE4EaLDD8qIyI2vOI3zbAqAluxyPtiTr0578eNgr61C1S RZDGJNIT1WNzLWhtAqu8A02TQOAHox+DjqWidZ8A6eMBNCnvwkiuMzYiTuiSQ+R2Qa4+ rhI3xi7NuQXl1YNCfHJwdb6KbZ0wkZANC8pr1dr77F0IiVCfrUxaJofMdtMJH+41hhM8 X5FEC3Ayhd75iF3w+BzrPyxdMQqNC6hZ67cAsor1aJZ+1+zKjL9qpsdSip3cvem84uB2 vLEw== X-Received: by 10.236.110.168 with SMTP id u28mr3070480yhg.40.1378391912190; Thu, 05 Sep 2013 07:38:32 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.49.37.170 with SMTP id z10ls292240qej.32.gmail; Thu, 05 Sep 2013 07:38:32 -0700 (PDT) X-Received: by 10.58.108.74 with SMTP id hi10mr8267565veb.14.1378391912031; Thu, 05 Sep 2013 07:38:32 -0700 (PDT) Received: from mail-ve0-f169.google.com (mail-ve0-f169.google.com [209.85.128.169]) by mx.google.com with ESMTPS id ee8si4557371vdc.2.1969.12.31.16.00.00 (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 05 Sep 2013 07:38:32 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.128.169 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=209.85.128.169; Received: by mail-ve0-f169.google.com with SMTP id db12so609807veb.0 for ; Thu, 05 Sep 2013 07:38:32 -0700 (PDT) X-Gm-Message-State: ALoCoQnM+yiWLX8cVtoCDqNWojJTh8zihvQSpmTL8HRM9S0/Nuq4qsyZkfsZgOkRtYklWE0y6Cfu X-Received: by 10.58.127.202 with SMTP id ni10mr900105veb.27.1378391911918; Thu, 05 Sep 2013 07:38:31 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.220.174.196 with SMTP id u4csp283833vcz; Thu, 5 Sep 2013 07:38:31 -0700 (PDT) X-Received: by 10.180.187.41 with SMTP id fp9mr6531604wic.33.1378391910252; Thu, 05 Sep 2013 07:38:30 -0700 (PDT) Received: from chiark.greenend.org.uk (v6.chiark.greenend.org.uk. [2001:ba8:1e3::]) by mx.google.com with ESMTPS id t7si3236615wiv.87.1969.12.31.16.00.00 (version=TLSv1 cipher=RC4-SHA bits=128/128); Thu, 05 Sep 2013 07:38:30 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pmaydell@chiark.greenend.org.uk designates 2001:ba8:1e3:: as permitted sender) client-ip=2001:ba8:1e3::; Received: by chiark.greenend.org.uk (Debian Exim 4.72 #1) with local (return-path pmaydell@chiark.greenend.org.uk) id 1VHahY-0005lX-T1; Thu, 05 Sep 2013 15:38:28 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Richard Henderson Subject: [PATCH v2 2/2] target-arm: Avoid "1 << 31" undefined behaviour Date: Thu, 5 Sep 2013 15:38:28 +0100 Message-Id: <1378391908-22137-3-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1378391908-22137-1-git-send-email-peter.maydell@linaro.org> References: <1378391908-22137-1-git-send-email-peter.maydell@linaro.org> Sender: Peter Maydell X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: peter.maydell@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.128.169 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Avoid the undefined behaviour of "1 << 31" by using 1U to make the shift be of an unsigned value rather than shifting into the sign bit of a signed integer. For consistency, we make all the CPSR_* constants unsigned, though the only one which triggers undefined behaviour is CPSR_N. Signed-off-by: Peter Maydell --- target-arm/cpu.h | 32 ++++++++++++++++---------------- target-arm/helper.c | 4 ++-- 2 files changed, 18 insertions(+), 18 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index f2abdf3..af7cf8a 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -270,22 +270,22 @@ int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address, int rw, int mmu_idx); #define cpu_handle_mmu_fault cpu_arm_handle_mmu_fault -#define CPSR_M (0x1f) -#define CPSR_T (1 << 5) -#define CPSR_F (1 << 6) -#define CPSR_I (1 << 7) -#define CPSR_A (1 << 8) -#define CPSR_E (1 << 9) -#define CPSR_IT_2_7 (0xfc00) -#define CPSR_GE (0xf << 16) -#define CPSR_RESERVED (0xf << 20) -#define CPSR_J (1 << 24) -#define CPSR_IT_0_1 (3 << 25) -#define CPSR_Q (1 << 27) -#define CPSR_V (1 << 28) -#define CPSR_C (1 << 29) -#define CPSR_Z (1 << 30) -#define CPSR_N (1 << 31) +#define CPSR_M (0x1fU) +#define CPSR_T (1U << 5) +#define CPSR_F (1U << 6) +#define CPSR_I (1U << 7) +#define CPSR_A (1U << 8) +#define CPSR_E (1U << 9) +#define CPSR_IT_2_7 (0xfc00U) +#define CPSR_GE (0xfU << 16) +#define CPSR_RESERVED (0xfU << 20) +#define CPSR_J (1U << 24) +#define CPSR_IT_0_1 (3U << 25) +#define CPSR_Q (1U << 27) +#define CPSR_V (1U << 28) +#define CPSR_C (1U << 29) +#define CPSR_Z (1U << 30) +#define CPSR_N (1U << 31) #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V) #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7) diff --git a/target-arm/helper.c b/target-arm/helper.c index e51ef20..c1a68c7 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -972,7 +972,7 @@ static int par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) static inline bool extended_addresses_enabled(CPUARMState *env) { return arm_feature(env, ARM_FEATURE_LPAE) - && (env->cp15.c2_control & (1 << 31)); + && (env->cp15.c2_control & (1U << 31)); } static int ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) @@ -1385,7 +1385,7 @@ static int mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri, * so these bits always RAZ. */ if (arm_feature(env, ARM_FEATURE_V7MP)) { - mpidr |= (1 << 31); + mpidr |= (1U << 31); /* Cores which are uniprocessor (non-coherent) * but still implement the MP extensions set * bit 30. (For instance, A9UP.) However we do