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[2001:ba8:1e3::]) by mx.google.com with ESMTPS id m20si7666125wiw.2.1969.12.31.16.00.00 (version=TLSv1 cipher=RC4-SHA bits=128/128); Tue, 03 Sep 2013 12:12:25 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pmaydell@chiark.greenend.org.uk designates 2001:ba8:1e3:: as permitted sender) client-ip=2001:ba8:1e3::; Received: by chiark.greenend.org.uk (Debian Exim 4.72 #1) with local (return-path pmaydell@chiark.greenend.org.uk) id 1VGw1Y-0005oH-F9; Tue, 03 Sep 2013 20:12:24 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Andreas Schwab , Alexander Graf , "Mian M. Hamayun" , kvmarm@lists.cs.columbia.edu, =?UTF-8?q?Andreas=20F=C3=A4rber?= Subject: [PATCH v6 11/24] target-arm: Add AArch64 gdbstub support Date: Tue, 3 Sep 2013 20:12:11 +0100 Message-Id: <1378235544-22290-12-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1378235544-22290-1-git-send-email-peter.maydell@linaro.org> References: <1378235544-22290-1-git-send-email-peter.maydell@linaro.org> Sender: Peter Maydell X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: peter.maydell@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.128.171 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Alexander Graf We want to be able to debug AArch64 guests. So let's add the respective gdb stub functions and xml descriptions that allow us to do so. Signed-off-by: Alexander Graf Signed-off-by: John Rigby Message-id: 1368505980-17151-6-git-send-email-john.rigby@linaro.org [PMM: dropped unused fp regs XML for now; moved 64 bit only functions to new gdbstub64.c; these are hooked up in AArch64CPU, not via ifdefs in ARMCPU] Signed-off-by: Peter Maydell --- gdb-xml/aarch64-core.xml | 46 +++++++++++++++++++++++++++++ target-arm/Makefile.objs | 2 +- target-arm/cpu-qom.h | 2 ++ target-arm/cpu64.c | 4 +++ target-arm/gdbstub64.c | 73 ++++++++++++++++++++++++++++++++++++++++++++++ 5 files changed, 126 insertions(+), 1 deletion(-) create mode 100644 gdb-xml/aarch64-core.xml create mode 100644 target-arm/gdbstub64.c diff --git a/gdb-xml/aarch64-core.xml b/gdb-xml/aarch64-core.xml new file mode 100644 index 0000000..e1e9dc3 --- /dev/null +++ b/gdb-xml/aarch64-core.xml @@ -0,0 +1,46 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/target-arm/Makefile.objs b/target-arm/Makefile.objs index a11d76e..6453f5c 100644 --- a/target-arm/Makefile.objs +++ b/target-arm/Makefile.objs @@ -5,4 +5,4 @@ obj-$(CONFIG_NO_KVM) += kvm-stub.o obj-y += translate.o op_helper.o helper.o cpu.o obj-y += neon_helper.o iwmmxt_helper.o obj-y += gdbstub.o -obj-$(TARGET_AARCH64) += cpu64.o translate-a64.o +obj-$(TARGET_AARCH64) += cpu64.o translate-a64.o gdbstub64.o diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h index 6502a7b..b55306a 100644 --- a/target-arm/cpu-qom.h +++ b/target-arm/cpu-qom.h @@ -176,6 +176,8 @@ void arm_gt_vtimer_cb(void *opaque); #ifdef TARGET_AARCH64 void aarch64_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, int flags); +int aarch64_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); +int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); #endif #endif diff --git a/target-arm/cpu64.c b/target-arm/cpu64.c index 4428f6c..3e99c21 100644 --- a/target-arm/cpu64.c +++ b/target-arm/cpu64.c @@ -73,6 +73,10 @@ static void aarch64_cpu_class_init(ObjectClass *oc, void *data) CPUClass *cc = CPU_CLASS(oc); cc->dump_state = aarch64_cpu_dump_state; + cc->gdb_read_register = aarch64_cpu_gdb_read_register; + cc->gdb_write_register = aarch64_cpu_gdb_write_register; + cc->gdb_num_core_regs = 34; + cc->gdb_core_xml_file = "aarch64-core.xml"; } static void aarch64_cpu_register(const ARMCPUInfo *info) diff --git a/target-arm/gdbstub64.c b/target-arm/gdbstub64.c new file mode 100644 index 0000000..7cb6a7c --- /dev/null +++ b/target-arm/gdbstub64.c @@ -0,0 +1,73 @@ +/* + * ARM gdb server stub: AArch64 specific functions. + * + * Copyright (c) 2013 SUSE LINUX Products GmbH + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ +#include "config.h" +#include "qemu-common.h" +#include "exec/gdbstub.h" + +int aarch64_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) +{ + ARMCPU *cpu = ARM_CPU(cs); + CPUARMState *env = &cpu->env; + + if (n < 31) { + /* Core integer register. */ + return gdb_get_reg64(mem_buf, env->xregs[n]); + } + switch (n) { + case 31: + return gdb_get_reg64(mem_buf, env->xregs[31]); + break; + case 32: + return gdb_get_reg64(mem_buf, env->pc); + break; + case 33: + return gdb_get_reg32(mem_buf, env->pstate); + } + /* Unknown register. */ + return 0; +} + +int aarch64_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) +{ + ARMCPU *cpu = ARM_CPU(cs); + CPUARMState *env = &cpu->env; + uint64_t tmp; + + tmp = ldq_p(mem_buf); + + if (n < 31) { + /* Core integer register. */ + env->xregs[n] = tmp; + return 8; + } + switch (n) { + case 31: + env->xregs[31] = tmp; + return 8; + case 32: + env->pc = tmp; + return 8; + case 33: + /* CPSR */ + env->pstate = tmp; + return 4; + } + /* Unknown register. */ + return 0; +}