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[2001:8b0:1d0::1]) by mx.google.com with ESMTPS id mu18si13886164pab.205.2013.08.09.09.18.03 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Fri, 09 Aug 2013 09:18:04 -0700 (PDT) Received-SPF: neutral (google.com: 2001:8b0:1d0::1 is neither permitted nor denied by best guess record for domain of pm215@archaic.org.uk) client-ip=2001:8b0:1d0::1; Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1V7pO4-0006wj-My; Fri, 09 Aug 2013 17:18:00 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, =?UTF-8?q?Andreas=20F=C3=A4rber?= Subject: [PATCH v2 4/4] hw/cpu/a15mpcore: Wire generic timer outputs to GIC inputs Date: Fri, 9 Aug 2013 17:18:00 +0100 Message-Id: <1376065080-26661-5-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1376065080-26661-1-git-send-email-peter.maydell@linaro.org> References: <1376065080-26661-1-git-send-email-peter.maydell@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: peter.maydell@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.212.43 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Now our A15 CPU implements the generic timers, we can wire them up to the appropriate inputs on the GIC. Signed-off-by: Peter Maydell Tested-by: Laurent Desnogues --- hw/cpu/a15mpcore.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/hw/cpu/a15mpcore.c b/hw/cpu/a15mpcore.c index 4f37964..af182da 100644 --- a/hw/cpu/a15mpcore.c +++ b/hw/cpu/a15mpcore.c @@ -49,6 +49,8 @@ static int a15mp_priv_init(SysBusDevice *dev) A15MPPrivState *s = A15MPCORE_PRIV(dev); SysBusDevice *busdev; const char *gictype = "arm_gic"; + int i; + CPUState *cpu; if (kvm_irqchip_in_kernel()) { gictype = "kvm-arm-gic"; @@ -67,6 +69,22 @@ static int a15mp_priv_init(SysBusDevice *dev) /* Pass through inbound GPIO lines to the GIC */ qdev_init_gpio_in(DEVICE(dev), a15mp_priv_set_irq, s->num_irq - 32); + /* Wire the outputs from each CPU's generic timer to the + * appropriate GIC PPI inputs + */ + for (i = 0, cpu = first_cpu; i < s->num_cpu; i++, cpu = cpu->next_cpu) { + DeviceState *cpudev = DEVICE(cpu); + int ppibase = s->num_irq - 32 + i * 32; + /* physical timer; we wire it up to the non-secure timer's ID, + * since a real A15 always has TrustZone but QEMU doesn't. + */ + qdev_connect_gpio_out(cpudev, 0, + qdev_get_gpio_in(s->gic, ppibase + 30)); + /* virtual timer */ + qdev_connect_gpio_out(cpudev, 1, + qdev_get_gpio_in(s->gic, ppibase + 27)); + } + /* Memory map (addresses are offsets from PERIPHBASE): * 0x0000-0x0fff -- reserved * 0x1000-0x1fff -- GIC Distributor