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[2001:8b0:1d0::1]) by mx.google.com with ESMTPS id l7si9308310lbd.65.2013.08.09.09.18.02 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Fri, 09 Aug 2013 09:18:02 -0700 (PDT) Received-SPF: neutral (google.com: 2001:8b0:1d0::1 is neither permitted nor denied by best guess record for domain of pm215@archaic.org.uk) client-ip=2001:8b0:1d0::1; Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1V7pO4-0006wX-9U; Fri, 09 Aug 2013 17:18:00 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, =?UTF-8?q?Andreas=20F=C3=A4rber?= Subject: [PATCH v2 1/4] target-arm: Allow raw_read() and raw_write() to handle 64 bit regs Date: Fri, 9 Aug 2013 17:17:57 +0100 Message-Id: <1376065080-26661-2-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1376065080-26661-1-git-send-email-peter.maydell@linaro.org> References: <1376065080-26661-1-git-send-email-peter.maydell@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: peter.maydell@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.220.169 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Extend the raw_read() and raw_write() helper accessors so that they can be used for 64 bit registers as well as 32 bit registers. Signed-off-by: Peter Maydell Tested-by: Laurent Desnogues Reviewed-by: Edgar E. Iglesias --- target-arm/helper.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index 4968391..fc5f757 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -67,14 +67,22 @@ static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) static int raw_read(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t *value) { - *value = CPREG_FIELD32(env, ri); + if (ri->type & ARM_CP_64BIT) { + *value = CPREG_FIELD64(env, ri); + } else { + *value = CPREG_FIELD32(env, ri); + } return 0; } static int raw_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - CPREG_FIELD32(env, ri) = value; + if (ri->type & ARM_CP_64BIT) { + CPREG_FIELD64(env, ri) = value; + } else { + CPREG_FIELD32(env, ri) = value; + } return 0; }