From patchwork Thu Aug 8 16:04:03 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 18898 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-qe0-f69.google.com (mail-qe0-f69.google.com [209.85.128.69]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 984A025E16 for ; Thu, 8 Aug 2013 16:04:34 +0000 (UTC) Received: by mail-qe0-f69.google.com with SMTP id 1sf3820822qec.8 for ; Thu, 08 Aug 2013 09:04:34 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=mime-version:x-gm-message-state:delivered-to:from:to:cc:subject :date:message-id:in-reply-to:references:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :list-post:list-help:list-archive:list-unsubscribe; bh=zD+/SXIz5jF17HDGrVbmsmTH6Xv97QnIPgBbi4Z8qJs=; b=VZLmyOej7IVTakQChCYUgLsQgtA9j950iJCD73qnAABY21y2V28ZOaBQ2JXgx2OKld U0QmnXdXop+Epl6e53N4nwDI32PQiKVRIMRz4uCvxNWGIC+u9zlUQ/hidqtpyBJjY0+m LMlgJqGGQL6yYTghrshh3RtsGfttSuMSrZH+L/DL9YLITvCpICgR5tspPihemR3mZHAJ nYWDO0azE0CdJ061kLDDAyhmN/0tuTTG8a6mStk3dUgvvLd6nwJS5Q11rD+7Ez/o3RZf bvgfEjDUWwEubpvzCEtZ/8P4BO79AmHdYbl/JW37mWDPCuZboT3uXKmwsgOmj2Kw+TvU i+7g== X-Received: by 10.236.130.148 with SMTP id k20mr3656189yhi.26.1375977874234; Thu, 08 Aug 2013 09:04:34 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.49.73.193 with SMTP id n1ls1148024qev.50.gmail; Thu, 08 Aug 2013 09:04:34 -0700 (PDT) X-Received: by 10.52.22.102 with SMTP id c6mr2988353vdf.33.1375977874094; Thu, 08 Aug 2013 09:04:34 -0700 (PDT) Received: from mail-ve0-f175.google.com (mail-ve0-f175.google.com [209.85.128.175]) by mx.google.com with ESMTPS id gq10si3271677vdc.147.2013.08.08.09.04.34 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 08 Aug 2013 09:04:34 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.128.175 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=209.85.128.175; Received: by mail-ve0-f175.google.com with SMTP id oy10so3166631veb.20 for ; Thu, 08 Aug 2013 09:04:34 -0700 (PDT) X-Gm-Message-State: ALoCoQlpttULVf7KdYLyGRWO+S3kKcOEPgZ1aI8mH7Js/oQ15CzkOi10Apvj9N3yF9HDI79/Yi2b X-Received: by 10.220.164.138 with SMTP id e10mr4435744vcy.27.1375977873976; Thu, 08 Aug 2013 09:04:33 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.220.174.196 with SMTP id u4csp23557vcz; Thu, 8 Aug 2013 09:04:33 -0700 (PDT) X-Received: by 10.14.205.72 with SMTP id i48mr8912069eeo.139.1375977871354; Thu, 08 Aug 2013 09:04:31 -0700 (PDT) Received: from mnementh.archaic.org.uk (1.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.d.1.0.0.b.8.0.1.0.0.2.ip6.arpa. [2001:8b0:1d0::1]) by mx.google.com with ESMTPS id n3si11451156eef.264.2013.08.08.09.04.30 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Thu, 08 Aug 2013 09:04:31 -0700 (PDT) Received-SPF: neutral (google.com: 2001:8b0:1d0::1 is neither permitted nor denied by best guess record for domain of pm215@archaic.org.uk) client-ip=2001:8b0:1d0::1; Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1V7ShE-0006WU-Nl; Thu, 08 Aug 2013 17:04:16 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, =?UTF-8?q?Andreas=20F=C3=A4rber?= Subject: [PATCH 01/14] target-arm: Make IRQ and FIQ gpio lines on the CPU object Date: Thu, 8 Aug 2013 17:04:03 +0100 Message-Id: <1375977856-25046-2-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1375977856-25046-1-git-send-email-peter.maydell@linaro.org> References: <1375977856-25046-1-git-send-email-peter.maydell@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: peter.maydell@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.128.175 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Now that ARMCPU is a subclass of DeviceState, we can make the CPU's inbound IRQ and FIQ lines be simply gpio lines, which means we can remove the odd arm_pic shim. We retain the arm_pic_init_cpu() function as a backwards compatibility shim layer so we can convert the board models to get the IRQ and FIQ lines directly from the ARMCPU object one at a time. Signed-off-by: Peter Maydell --- hw/arm/pic_cpu.c | 63 +++++++++--------------------------------------------- target-arm/cpu.c | 60 +++++++++++++++++++++++++++++++++++++++++++++++++++ target-arm/cpu.h | 3 +++ 3 files changed, 73 insertions(+), 53 deletions(-) diff --git a/hw/arm/pic_cpu.c b/hw/arm/pic_cpu.c index 875280a..9c36273 100644 --- a/hw/arm/pic_cpu.c +++ b/hw/arm/pic_cpu.c @@ -9,60 +9,17 @@ #include "hw/hw.h" #include "hw/arm/arm.h" -#include "sysemu/kvm.h" - -/* Input 0 is IRQ and input 1 is FIQ. */ -static void arm_pic_cpu_handler(void *opaque, int irq, int level) -{ - ARMCPU *cpu = opaque; - CPUState *cs = CPU(cpu); - - switch (irq) { - case ARM_PIC_CPU_IRQ: - if (level) { - cpu_interrupt(cs, CPU_INTERRUPT_HARD); - } else { - cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); - } - break; - case ARM_PIC_CPU_FIQ: - if (level) { - cpu_interrupt(cs, CPU_INTERRUPT_FIQ); - } else { - cpu_reset_interrupt(cs, CPU_INTERRUPT_FIQ); - } - break; - default: - hw_error("arm_pic_cpu_handler: Bad interrupt line %d\n", irq); - } -} - -static void kvm_arm_pic_cpu_handler(void *opaque, int irq, int level) -{ -#ifdef CONFIG_KVM - ARMCPU *cpu = opaque; - CPUState *cs = CPU(cpu); - int kvm_irq = KVM_ARM_IRQ_TYPE_CPU << KVM_ARM_IRQ_TYPE_SHIFT; - - switch (irq) { - case ARM_PIC_CPU_IRQ: - kvm_irq |= KVM_ARM_IRQ_CPU_IRQ; - break; - case ARM_PIC_CPU_FIQ: - kvm_irq |= KVM_ARM_IRQ_CPU_FIQ; - break; - default: - hw_error("kvm_arm_pic_cpu_handler: Bad interrupt line %d\n", irq); - } - kvm_irq |= cs->cpu_index << KVM_ARM_IRQ_VCPU_SHIFT; - kvm_set_irq(kvm_state, kvm_irq, level ? 1 : 0); -#endif -} +/* Backwards compatibility shim; this can disappear when all + * board models have been updated to get IRQ and FIQ lines directly + * from the ARMCPU object rather than by calling this function. + */ qemu_irq *arm_pic_init_cpu(ARMCPU *cpu) { - if (kvm_enabled()) { - return qemu_allocate_irqs(kvm_arm_pic_cpu_handler, cpu, 2); - } - return qemu_allocate_irqs(arm_pic_cpu_handler, cpu, 2); + DeviceState *dev = DEVICE(cpu); + qemu_irq *irqs = g_new(qemu_irq, 2); + + irqs[0] = qdev_get_gpio_in(dev, ARM_CPU_IRQ); + irqs[1] = qdev_get_gpio_in(dev, ARM_CPU_FIQ); + return irqs; } diff --git a/target-arm/cpu.c b/target-arm/cpu.c index 5a7566b..6f56aa8 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -23,7 +23,9 @@ #if !defined(CONFIG_USER_ONLY) #include "hw/loader.h" #endif +#include "hw/arm/arm.h" #include "sysemu/sysemu.h" +#include "sysemu/kvm.h" static void arm_cpu_set_pc(CPUState *cs, vaddr value) { @@ -129,6 +131,55 @@ static void arm_cpu_reset(CPUState *s) tb_flush(env); } +#ifndef CONFIG_USER_ONLY +static void arm_cpu_set_irq(void *opaque, int irq, int level) +{ + ARMCPU *cpu = opaque; + CPUState *cs = CPU(cpu); + + switch (irq) { + case ARM_CPU_IRQ: + if (level) { + cpu_interrupt(cs, CPU_INTERRUPT_HARD); + } else { + cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); + } + break; + case ARM_CPU_FIQ: + if (level) { + cpu_interrupt(cs, CPU_INTERRUPT_FIQ); + } else { + cpu_reset_interrupt(cs, CPU_INTERRUPT_FIQ); + } + break; + default: + hw_error("arm_cpu_set_irq: Bad interrupt line %d\n", irq); + } +} + +static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level) +{ +#ifdef CONFIG_KVM + ARMCPU *cpu = opaque; + CPUState *cs = CPU(cpu); + int kvm_irq = KVM_ARM_IRQ_TYPE_CPU << KVM_ARM_IRQ_TYPE_SHIFT; + + switch (irq) { + case ARM_CPU_IRQ: + kvm_irq |= KVM_ARM_IRQ_CPU_IRQ; + break; + case ARM_CPU_FIQ: + kvm_irq |= KVM_ARM_IRQ_CPU_FIQ; + break; + default: + hw_error("arm_cpu_kvm_set_irq: Bad interrupt line %d\n", irq); + } + kvm_irq |= cs->cpu_index << KVM_ARM_IRQ_VCPU_SHIFT; + kvm_set_irq(kvm_state, kvm_irq, level ? 1 : 0); +#endif +} +#endif + static inline void set_feature(CPUARMState *env, int feature) { env->features |= 1ULL << feature; @@ -145,6 +196,15 @@ static void arm_cpu_initfn(Object *obj) cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal, g_free, g_free); +#ifndef CONFIG_USER_ONLY + /* Our inbound IRQ and FIQ lines */ + if (kvm_enabled()) { + qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 2); + } else { + qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 2); + } +#endif + if (tcg_enabled() && !inited) { inited = true; arm_translate_init(); diff --git a/target-arm/cpu.h b/target-arm/cpu.h index b2dc494..dffeec7 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -58,6 +58,9 @@ /* ARM-specific interrupt pending bits. */ #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 +/* Meanings of the ARMCPU object's two inbound GPIO lines */ +#define ARM_CPU_IRQ 0 +#define ARM_CPU_FIQ 1 typedef void ARMWriteCPFunc(void *opaque, int cp_info, int srcreg, int operand, uint32_t value);