From patchwork Thu Jul 25 16:42:03 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 18585 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-ye0-f199.google.com (mail-ye0-f199.google.com [209.85.213.199]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id E8AB725E88 for ; Thu, 25 Jul 2013 16:42:11 +0000 (UTC) Received: by mail-ye0-f199.google.com with SMTP id l12sf754325yen.2 for ; Thu, 25 Jul 2013 09:42:11 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=mime-version:x-beenthere:x-forwarded-to:x-forwarded-for :delivered-to:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references:x-gm-message-state:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :x-google-group-id:list-post:list-help:list-archive:list-unsubscribe; bh=loF3EXY00AbKeGnJGItuL8WlHdElB/xG22eRPQH8RZE=; b=ZQCwFZ0zrvJcrnwqbyQw6SvqmtOcIVtmZx8bkNfL2dnWllUBHLjEV/cZnaJSE6mc/d uyMrKYgfRTqvu6uSXhSKlYSS+DhbFoooKCtSXvR3/XDZdnhUB2yo6EXhkBlsZRBVh3gx bWhvGVN2hyBFqhJacmoJ+AKumuXl+ZlDMInlsJwH3yenhqFUwYRvGq6cdcaNi7kc2Vcz ZvsIyn/9qCO8t60nJmY+qJUo3HzdK+DzeK3IZKOVjCYCulHBNrEGEMEk1EveP3Pzx8TB ZbhkpHv4u8hnm7OGU5pwiHa5WDuk8EDo7KZaPlz9TKCZ5oD532B2aJd/x4jOg8hlKTRj kyGQ== X-Received: by 10.236.54.8 with SMTP id h8mr23799876yhc.11.1374770531563; Thu, 25 Jul 2013 09:42:11 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.49.12.233 with SMTP id b9ls681185qec.14.gmail; Thu, 25 Jul 2013 09:42:11 -0700 (PDT) X-Received: by 10.52.165.239 with SMTP id zb15mr15221141vdb.44.1374770531473; Thu, 25 Jul 2013 09:42:11 -0700 (PDT) Received: from mail-vb0-f50.google.com (mail-vb0-f50.google.com [209.85.212.50]) by mx.google.com with ESMTPS id k4si12626036vdi.28.2013.07.25.09.42.11 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 25 Jul 2013 09:42:11 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.212.50 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=209.85.212.50; Received: by mail-vb0-f50.google.com with SMTP id x13so156334vbb.23 for ; Thu, 25 Jul 2013 09:42:11 -0700 (PDT) X-Received: by 10.220.203.197 with SMTP id fj5mr1066510vcb.60.1374770531323; Thu, 25 Jul 2013 09:42:11 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.58.165.8 with SMTP id yu8csp86319veb; Thu, 25 Jul 2013 09:42:10 -0700 (PDT) X-Received: by 10.205.39.196 with SMTP id tn4mr6341755bkb.183.1374770528383; Thu, 25 Jul 2013 09:42:08 -0700 (PDT) Received: from mnementh.archaic.org.uk (1.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.d.1.0.0.b.8.0.1.0.0.2.ip6.arpa. [2001:8b0:1d0::1]) by mx.google.com with ESMTPS id tv3si5941604bkb.306.2013.07.25.09.42.07 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Thu, 25 Jul 2013 09:42:07 -0700 (PDT) Received-SPF: neutral (google.com: 2001:8b0:1d0::1 is neither permitted nor denied by best guess record for domain of pm215@archaic.org.uk) client-ip=2001:8b0:1d0::1; Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1V2Oc8-0001iZ-6u; Thu, 25 Jul 2013 17:42:04 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Anthony Liguori , =?UTF-8?q?Andreas=20F=C3=A4rber?= , Alexander Graf Subject: [RFC 2/2] arm_gic: Use new __private macro to mark private fields Date: Thu, 25 Jul 2013 17:42:03 +0100 Message-Id: <1374770523-6570-3-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1374770523-6570-1-git-send-email-peter.maydell@linaro.org> References: <1374770523-6570-1-git-send-email-peter.maydell@linaro.org> X-Gm-Message-State: ALoCoQluHaHseLZ3fNk7+3uJKScJjeJmDq3O5nT1cSnMnOFTuYeXXB65DDpviytHKcf4mk7bG+LI X-Original-Sender: peter.maydell@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.212.50 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Use the new __private macro infrastructure to mark private fields for the arm_gic classes. Signed-off-by: Peter Maydell --- hw/intc/arm_gic.c | 3 +++ hw/intc/arm_gic_common.c | 2 ++ hw/intc/arm_gic_kvm.c | 2 ++ hw/intc/armv7m_nvic.c | 2 ++ include/hw/intc/arm_gic.h | 64 ++++++++++++++++++++++++++++----------------- 5 files changed, 49 insertions(+), 24 deletions(-) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index 8e34004..cbe7d27 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -18,6 +18,9 @@ * armv7m_nvic device. */ +#define IMPLEMENTING_ARM_GIC_COMMON +#define IMPLEMENTING_ARM_GIC + #include "hw/sysbus.h" #include "gic_internal.h" #include "qom/cpu.h" diff --git a/hw/intc/arm_gic_common.c b/hw/intc/arm_gic_common.c index a89c786..c27c5c1 100644 --- a/hw/intc/arm_gic_common.c +++ b/hw/intc/arm_gic_common.c @@ -18,6 +18,8 @@ * with this program; if not, see . */ +#define IMPLEMENTING_ARM_GIC_COMMON + #include "gic_internal.h" static void gic_pre_save(void *opaque) diff --git a/hw/intc/arm_gic_kvm.c b/hw/intc/arm_gic_kvm.c index f713975..0acd676 100644 --- a/hw/intc/arm_gic_kvm.c +++ b/hw/intc/arm_gic_kvm.c @@ -18,6 +18,8 @@ * with this program; if not, see . */ +#define IMPLEMENTING_ARM_GIC_COMMON + #include "hw/sysbus.h" #include "sysemu/kvm.h" #include "kvm_arm.h" diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 178344b..54d62fe 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -10,6 +10,8 @@ * NVIC. Much of that is also implemented here. */ +#define IMPLEMENTING_ARM_GIC_COMMON + #include "hw/sysbus.h" #include "qemu/timer.h" #include "hw/arm/arm.h" diff --git a/include/hw/intc/arm_gic.h b/include/hw/intc/arm_gic.h index be945ec..d978d72 100644 --- a/include/hw/intc/arm_gic.h +++ b/include/hw/intc/arm_gic.h @@ -40,36 +40,42 @@ typedef struct gic_irq_state { bool trigger; /* nonzero = edge triggered. */ } gic_irq_state; +#ifdef IMPLEMENTING_ARM_GIC_COMMON +#define __private +#else +#define __private QEMU_PRIVATE_ATTR +#endif + typedef struct GICState { /*< private >*/ - SysBusDevice busdev; + __private SysBusDevice busdev; /*< public >*/ - qemu_irq parent_irq[GIC_NCPU]; - bool enabled; - bool cpu_enabled[GIC_NCPU]; + __private qemu_irq parent_irq[GIC_NCPU]; + __private bool enabled; + __private bool cpu_enabled[GIC_NCPU]; - gic_irq_state irq_state[GIC_MAXIRQ]; - uint8_t irq_target[GIC_MAXIRQ]; - uint8_t priority1[GIC_INTERNAL][GIC_NCPU]; - uint8_t priority2[GIC_MAXIRQ - GIC_INTERNAL]; - uint16_t last_active[GIC_MAXIRQ][GIC_NCPU]; + __private gic_irq_state irq_state[GIC_MAXIRQ]; + __private uint8_t irq_target[GIC_MAXIRQ]; + __private uint8_t priority1[GIC_INTERNAL][GIC_NCPU]; + __private uint8_t priority2[GIC_MAXIRQ - GIC_INTERNAL]; + __private uint16_t last_active[GIC_MAXIRQ][GIC_NCPU]; - uint16_t priority_mask[GIC_NCPU]; - uint16_t running_irq[GIC_NCPU]; - uint16_t running_priority[GIC_NCPU]; - uint16_t current_pending[GIC_NCPU]; + __private uint16_t priority_mask[GIC_NCPU]; + __private uint16_t running_irq[GIC_NCPU]; + __private uint16_t running_priority[GIC_NCPU]; + __private uint16_t current_pending[GIC_NCPU]; - uint32_t num_cpu; + __private uint32_t num_cpu; - MemoryRegion iomem; /* Distributor */ + __private MemoryRegion iomem; /* Distributor */ /* This is just so we can have an opaque pointer which identifies * both this GIC and which CPU interface we should be accessing. */ - struct GICState *backref[GIC_NCPU]; - MemoryRegion cpuiomem[GIC_NCPU + 1]; /* CPU interfaces */ - uint32_t num_irq; - uint32_t revision; + __private struct GICState *backref[GIC_NCPU]; + __private MemoryRegion cpuiomem[GIC_NCPU + 1]; /* CPU interfaces */ + __private uint32_t num_irq; + __private uint32_t revision; } GICState; #define TYPE_ARM_GIC_COMMON "arm_gic_common" @@ -82,13 +88,21 @@ typedef struct GICState { typedef struct ARMGICCommonClass { /*< private >*/ - SysBusDeviceClass parent_class; + __private SysBusDeviceClass parent_class; /*< public >*/ - void (*pre_save)(GICState *s); - void (*post_load)(GICState *s); + __private void (*pre_save)(GICState *s); + __private void (*post_load)(GICState *s); } ARMGICCommonClass; +#undef __private + +#ifdef IMPLEMENTING_ARM_GIC +#define __private +#else +#define __private QEMU_PRIVATE_ATTR +#endif + #define TYPE_ARM_GIC "arm_gic" #define ARM_GIC(obj) \ OBJECT_CHECK(GICState, (obj), TYPE_ARM_GIC) @@ -99,10 +113,12 @@ typedef struct ARMGICCommonClass { typedef struct ARMGICClass { /*< private >*/ - ARMGICCommonClass parent_class; + __private ARMGICCommonClass parent_class; /*< public >*/ - DeviceRealize parent_realize; + __private DeviceRealize parent_realize; } ARMGICClass; +#undef __private + #endif