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[2001:8b0:1d0::1]) by mx.google.com with ESMTPS id x6si6758538lbq.63.2013.07.01.10.35.23 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Mon, 01 Jul 2013 10:35:23 -0700 (PDT) Received-SPF: neutral (google.com: 2001:8b0:1d0::1 is neither permitted nor denied by best guess record for domain of pm215@archaic.org.uk) client-ip=2001:8b0:1d0::1; Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1Uti0X-0002KD-Cc; Mon, 01 Jul 2013 18:35:21 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Alexander Graf , Andreas Schwab , "Mian M. Hamayun" Subject: [PATCH v5 04/21] target-arm: Fix target_ulong/uint32_t confusions Date: Mon, 1 Jul 2013 18:35:03 +0100 Message-Id: <1372700120-8896-5-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1372700120-8896-1-git-send-email-peter.maydell@linaro.org> References: <1372700120-8896-1-git-send-email-peter.maydell@linaro.org> X-Gm-Message-State: ALoCoQnzxN4bMxKef4gxyIE+KExuRk9gjZno/T24mlAGvvSDXDEC6MMadTu4LgdBiVAwKXB+hzhI X-Original-Sender: peter.maydell@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.212.47 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Alexander Graf Correct a few places that were using uint32_t or a 32 bit only format string to handle something that should be a target_ulong. Signed-off-by: Alexander Graf Signed-off-by: John Rigby [PMM: split out to separate patch; added gen_goto_tb() and gen_set_pc_im() dest params to list of things to change.] Signed-off-by: Peter Maydell --- target-arm/cpu.h | 4 ++-- target-arm/translate.c | 9 +++++---- 2 files changed, 7 insertions(+), 6 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index abcc0b4..1f3beac 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -816,7 +816,7 @@ static inline void cpu_pc_from_tb(CPUARMState *env, TranslationBlock *tb) } /* Load an instruction and return it in the standard little-endian order */ -static inline uint32_t arm_ldl_code(CPUARMState *env, uint32_t addr, +static inline uint32_t arm_ldl_code(CPUARMState *env, target_ulong addr, bool do_swap) { uint32_t insn = cpu_ldl_code(env, addr); @@ -827,7 +827,7 @@ static inline uint32_t arm_ldl_code(CPUARMState *env, uint32_t addr, } /* Ditto, for a halfword (Thumb) instruction */ -static inline uint16_t arm_lduw_code(CPUARMState *env, uint32_t addr, +static inline uint16_t arm_lduw_code(CPUARMState *env, target_ulong addr, bool do_swap) { uint16_t insn = cpu_lduw_code(env, addr); diff --git a/target-arm/translate.c b/target-arm/translate.c index a6c2cf9..02319b3 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -903,7 +903,7 @@ DO_GEN_ST(st8) DO_GEN_ST(st16) DO_GEN_ST(st32) -static inline void gen_set_pc_im(uint32_t val) +static inline void gen_set_pc_im(target_ulong val) { tcg_gen_movi_i32(cpu_R[15], val); } @@ -3411,7 +3411,7 @@ static int disas_vfp_insn(CPUARMState * env, DisasContext *s, uint32_t insn) return 0; } -static inline void gen_goto_tb(DisasContext *s, int n, uint32_t dest) +static inline void gen_goto_tb(DisasContext *s, int n, target_ulong dest) { TranslationBlock *tb; @@ -9869,7 +9869,7 @@ static inline void gen_intermediate_code_internal(CPUARMState *env, uint16_t *gen_opc_end; int j, lj; target_ulong pc_start; - uint32_t next_page_start; + target_ulong next_page_start; int num_insns; int max_insns; @@ -10023,7 +10023,8 @@ static inline void gen_intermediate_code_internal(CPUARMState *env, } if (tcg_check_temp_count()) { - fprintf(stderr, "TCG temporary leak before %08x\n", dc->pc); + fprintf(stderr, "TCG temporary leak before "TARGET_FMT_lx"\n", + dc->pc); } /* Translation stops when a conditional branch is encountered.