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[2001:8b0:1d0::1]) by mx.google.com with ESMTPS id v7si11961613eew.306.2013.07.01.10.35.25 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Mon, 01 Jul 2013 10:35:25 -0700 (PDT) Received-SPF: neutral (google.com: 2001:8b0:1d0::1 is neither permitted nor denied by best guess record for domain of pm215@archaic.org.uk) client-ip=2001:8b0:1d0::1; Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1Uti0a-0002Lm-3T; Mon, 01 Jul 2013 18:35:24 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Alexander Graf , Andreas Schwab , "Mian M. Hamayun" Subject: [PATCH v5 15/21] target-arm: Implement cpu_set_tls() and cpu_clone_regs() for AArch64 Date: Mon, 1 Jul 2013 18:35:14 +0100 Message-Id: <1372700120-8896-16-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1372700120-8896-1-git-send-email-peter.maydell@linaro.org> References: <1372700120-8896-1-git-send-email-peter.maydell@linaro.org> X-Gm-Message-State: ALoCoQkJum3VLTrnCZ4tEhXeRlp8UBObTGeyGe7egClpsnhrnfAUut1lScYHaf9EhgNgzxjlmdro X-Original-Sender: peter.maydell@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.128.177 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Alexander Graf [PMM: pulled out from another patch because this is going to need to morph into a patch putting them into linux-user/aarch64/target_cpu.h as soon as my patch doing that move for existing CPUs lands; also use #ifdefs rather than is_a64().] Signed-off-by: Alexander Graf Signed-off-by: John Rigby Signed-off-by: Peter Maydell --- target-arm/cpu.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 78614a4..f9288d1 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -303,10 +303,17 @@ int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address, int rw, int mmu_idx); #define cpu_handle_mmu_fault cpu_arm_handle_mmu_fault +#ifndef TARGET_AARCH64 static inline void cpu_set_tls(CPUARMState *env, target_ulong newtls) { env->cp15.c13_tls2 = newtls; } +#else +static inline void cpu_set_tls(CPUARMState *env, target_ulong newtls) +{ + env->sr.tpidr_el0 = newtls; +} +#endif #define CPSR_M (0x1f) #define CPSR_T (1 << 5) @@ -795,12 +802,22 @@ static inline int cpu_mmu_index (CPUARMState *env) } #if defined(CONFIG_USER_ONLY) +#ifndef TARGET_AARCH64 static inline void cpu_clone_regs(CPUARMState *env, target_ulong newsp) { if (newsp) env->regs[13] = newsp; env->regs[0] = 0; } +#else +static inline void cpu_clone_regs(CPUARMState *env, target_ulong newsp) +{ + if (newsp) { + env->xregs[31] = newsp; + } + env->xregs[0] = 0; +} +#endif #endif #include "exec/cpu-all.h"