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[2001:8b0:1d0::1]) by mx.google.com with ESMTPS id t2si22456202wjf.156.2013.06.04.06.31.46 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Tue, 04 Jun 2013 06:31:47 -0700 (PDT) Received-SPF: neutral (google.com: 2001:8b0:1d0::1 is neither permitted nor denied by best guess record for domain of pm215@archaic.org.uk) client-ip=2001:8b0:1d0::1; Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1UjrKz-0007BR-ST; Tue, 04 Jun 2013 14:31:45 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH] user-exec.c: Set is_write correctly in the ARM cpu_signal_handler() Date: Tue, 4 Jun 2013 14:31:45 +0100 Message-Id: <1370352705-27590-1-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 X-Gm-Message-State: ALoCoQle/Wqg7PePnYyERDwDjt0JwaXIvkHTouOXnZCkQeg6gvMoLxf1gWMbIIaUv4aV++4dsIAu X-Original-Sender: peter.maydell@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 2607:f8b0:400c:c01::22e is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , In the ARM implementation of cpu_signal_handler(), set is_write correctly using the FSR value which the kernel passes us in the error_code field of uc_mcontext. Since the WnR bit of the FSR was only introduced in ARMv6, this means that v5 cores will continue to behave as before this patch, but they are not really supported as hosts for linux-user mode anyway since they do not have the modern behaviour for unaligned accesses. Signed-off-by: Peter Maydell Acked-by: Alexander Graf --- Without this linux-user won't work very well. In particular after fork() bash will segfault, with this in the QEMU_STRACE output immediately preceding: sigreturn(18,4390912,1082130608,0,0,0) = -1 errno=255 (Unknown error 255) at least for PPC and MIPSEL guests. user-exec.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/user-exec.c b/user-exec.c index 71bd6c5..336ac70 100644 --- a/user-exec.c +++ b/user-exec.c @@ -20,6 +20,7 @@ #include "cpu.h" #include "disas/disas.h" #include "tcg.h" +#include "qemu/bitops.h" #undef EAX #undef ECX @@ -441,8 +442,11 @@ int cpu_signal_handler(int host_signum, void *pinfo, #else pc = uc->uc_mcontext.arm_pc; #endif - /* XXX: compute is_write */ - is_write = 0; + + /* error_code is the FSR value, in which bit 11 is WnR (assuming a v6 or + * later processor; on v5 we will always report this as a read). + */ + is_write = extract32(uc->uc_mcontext.error_code, 11, 1); return handle_cpu_signal(pc, (unsigned long)info->si_addr, is_write, &uc->uc_sigmask, puc);