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[2001:8b0:1d0::1]) by mx.google.com with ESMTPS id tr1si9885550pab.239.2013.03.24.04.32.44 (version=TLSv1 cipher=RC4-SHA bits=128/128); Sun, 24 Mar 2013 04:32:45 -0700 (PDT) Received-SPF: neutral (google.com: 2001:8b0:1d0::1 is neither permitted nor denied by best guess record for domain of pm215@archaic.org.uk) client-ip=2001:8b0:1d0::1; Authentication-Results: mx.google.com; spf=neutral (google.com: 2001:8b0:1d0::1 is neither permitted nor denied by best guess record for domain of pm215@archaic.org.uk) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1UJjAG-0001Vx-5U; Sun, 24 Mar 2013 11:32:40 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, =?UTF-8?q?Andreas=20F=C3=A4rber?= , "Michael S. Tsirkin" , Paul Brook , Arnd Bergmann , Will Deacon Subject: [PATCH 02/10] versatile_pci: Expose PCI I/O region on Versatile PB Date: Sun, 24 Mar 2013 11:32:32 +0000 Message-Id: <1364124760-5794-3-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1364124760-5794-1-git-send-email-peter.maydell@linaro.org> References: <1364124760-5794-1-git-send-email-peter.maydell@linaro.org> X-Gm-Message-State: ALoCoQn2exs+Rk5LVzvJq2Gs+EOcmNFS0AaZZhrtB/I9ekeRv4KuuOsq3A3TFA9F2WH8Rlp8I9Kg Comments in the QEMU source code claim that the version of the PCI controller on the VersatilePB board doesn't support the PCI I/O region, but this is incorrect; expose that region, map it in the correct location, and drop the misleading comments. This change removes the only currently implemented difference between the realview-pci and versatile-pci models; however there are other differences in not-yet-implemented functionality, so we retain the distinction between the two device types. Signed-off-by: Peter Maydell --- hw/arm/versatilepb.c | 3 +-- hw/versatile_pci.c | 8 +++----- 2 files changed, 4 insertions(+), 7 deletions(-) diff --git a/hw/arm/versatilepb.c b/hw/arm/versatilepb.c index baaa265..0d08d15 100644 --- a/hw/arm/versatilepb.c +++ b/hw/arm/versatilepb.c @@ -226,14 +226,13 @@ static void versatile_init(QEMUMachineInitArgs *args, int board_id) qdev_init_nofail(dev); sysbus_mmio_map(busdev, 0, 0x41000000); /* PCI self-config */ sysbus_mmio_map(busdev, 1, 0x42000000); /* PCI config */ + sysbus_mmio_map(busdev, 2, 0x43000000); /* PCI I/O */ sysbus_connect_irq(busdev, 0, sic[27]); sysbus_connect_irq(busdev, 1, sic[28]); sysbus_connect_irq(busdev, 2, sic[29]); sysbus_connect_irq(busdev, 3, sic[30]); pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci"); - /* The Versatile PCI bridge does not provide access to PCI IO space, - so many of the qemu PCI devices are not useable. */ for(n = 0; n < nb_nics; n++) { nd = &nd_table[n]; diff --git a/hw/versatile_pci.c b/hw/versatile_pci.c index 16ce5d1..1312f46 100644 --- a/hw/versatile_pci.c +++ b/hw/versatile_pci.c @@ -77,7 +77,7 @@ static int pci_vpb_init(SysBusDevice *dev) /* Our memory regions are: * 0 : PCI self config window * 1 : PCI config window - * 2 : PCI IO window (realview_pci only) + * 2 : PCI IO window */ memory_region_init_io(&s->mem_config, &pci_vpb_config_ops, bus, "pci-vpb-selfconfig", 0x1000000); @@ -85,10 +85,8 @@ static int pci_vpb_init(SysBusDevice *dev) memory_region_init_io(&s->mem_config2, &pci_vpb_config_ops, bus, "pci-vpb-config", 0x1000000); sysbus_init_mmio(dev, &s->mem_config2); - if (s->realview) { - isa_mmio_setup(&s->isa, 0x0100000); - sysbus_init_mmio(dev, &s->isa); - } + isa_mmio_setup(&s->isa, 0x0100000); + sysbus_init_mmio(dev, &s->isa); pci_create_simple(bus, -1, "versatile_pci_host"); return 0;