From patchwork Mon Mar 18 16:30:37 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 15409 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 1FABC23E75 for ; Mon, 18 Mar 2013 16:30:43 +0000 (UTC) Received: from mail-vc0-f181.google.com (mail-vc0-f181.google.com [209.85.220.181]) by fiordland.canonical.com (Postfix) with ESMTP id 9AFAAA184C0 for ; Mon, 18 Mar 2013 16:30:42 +0000 (UTC) Received: by mail-vc0-f181.google.com with SMTP id hv10so3075023vcb.40 for ; Mon, 18 Mar 2013 09:30:42 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:x-forwarded-to:x-forwarded-for:delivered-to:x-received :received-spf:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references:x-gm-message-state; bh=GlRECyPzgVdh2qXHuqkErW/K9gehTxySZu4T6yWypNs=; b=d33xaDE+Whsv9fS9X1w7J0FsJrnTPOY4sn1kJ6RBIlNSKug094p7J0LYdLJMcIJ/V5 HrG7zPFBNv26PhaxGYvSOnMyldEHTZ5s1jJz2meiHBIx5+GdwH7/gc6nAT6NQKgXrO+T sbd/98Sd6408wqUK4uohUX7DXs6zBvUsrvHm8YFjKfgIIfdcUUsKVTsxhzbgyV0P8FEz VgMPLnlRd29EH8OPiGsCJLVPgcv153G+tiNrI543TDqW3D6gyLtMh9BtAXIG+/gGtRd1 0wKT2o0amLiCjLY8n5bI10GEwG3aujMi4cLgbrBK/fi7NO16JfBsqDS7XciGIiYseD5h s+ww== X-Received: by 10.58.84.164 with SMTP id a4mr21199313vez.9.1363624241666; Mon, 18 Mar 2013 09:30:41 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.58.127.98 with SMTP id nf2csp33646veb; Mon, 18 Mar 2013 09:30:40 -0700 (PDT) X-Received: by 10.204.202.133 with SMTP id fe5mr7312889bkb.59.1363624239756; Mon, 18 Mar 2013 09:30:39 -0700 (PDT) Received: from mnementh.archaic.org.uk (1.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.d.1.0.0.b.8.0.1.0.0.2.ip6.arpa. [2001:8b0:1d0::1]) by mx.google.com with ESMTPS id ii11si5000228bkc.172.2013.03.18.09.30.39 (version=TLSv1 cipher=RC4-SHA bits=128/128); Mon, 18 Mar 2013 09:30:39 -0700 (PDT) Received-SPF: neutral (google.com: 2001:8b0:1d0::1 is neither permitted nor denied by best guess record for domain of pm215@archaic.org.uk) client-ip=2001:8b0:1d0::1; Authentication-Results: mx.google.com; spf=neutral (google.com: 2001:8b0:1d0::1 is neither permitted nor denied by best guess record for domain of pm215@archaic.org.uk) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1UHcxK-0007aA-6l; Mon, 18 Mar 2013 16:30:38 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH 1/2] arm_gic: Fix sizes of state fields in preparation for vmstate support Date: Mon, 18 Mar 2013 16:30:37 +0000 Message-Id: <1363624238-29121-2-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1363624238-29121-1-git-send-email-peter.maydell@linaro.org> References: <1363624238-29121-1-git-send-email-peter.maydell@linaro.org> X-Gm-Message-State: ALoCoQlirUzbjbhnZoWv9+yBLDowcbnqmznMTF1ILa9papyMuqMShU4n6bjCPDqsh2pvD5wfcRq9 In preparation for switching to vmstate for migration support, fix the sizes of various GIC state fields. In particular, we replace all the bitfields (which VMState can't deal with) with straightforward uint8_t values which we do bit operations on. (The bitfields made more sense when NCPU was set differently in different situations, but we now always model at the architectural limit of 8.) Signed-off-by: Peter Maydell --- hw/arm_gic_common.c | 4 ++-- hw/arm_gic_internal.h | 42 +++++++++++++++++++++--------------------- hw/armv7m_nvic.c | 4 ++-- 3 files changed, 25 insertions(+), 25 deletions(-) diff --git a/hw/arm_gic_common.c b/hw/arm_gic_common.c index f2dc8bf..f95bec3 100644 --- a/hw/arm_gic_common.c +++ b/hw/arm_gic_common.c @@ -149,7 +149,7 @@ static void arm_gic_common_reset(DeviceState *dev) s->current_pending[i] = 1023; s->running_irq[i] = 1023; s->running_priority[i] = 0x100; - s->cpu_enabled[i] = 0; + s->cpu_enabled[i] = false; } for (i = 0; i < 16; i++) { GIC_SET_ENABLED(i, ALL_CPU_MASK); @@ -161,7 +161,7 @@ static void arm_gic_common_reset(DeviceState *dev) s->irq_target[i] = 1; } } - s->enabled = 0; + s->enabled = false; } static Property arm_gic_common_properties[] = { diff --git a/hw/arm_gic_internal.h b/hw/arm_gic_internal.h index 3e1928b..99a3bc3 100644 --- a/hw/arm_gic_internal.h +++ b/hw/arm_gic_internal.h @@ -45,14 +45,14 @@ #define GIC_SET_ACTIVE(irq, cm) s->irq_state[irq].active |= (cm) #define GIC_CLEAR_ACTIVE(irq, cm) s->irq_state[irq].active &= ~(cm) #define GIC_TEST_ACTIVE(irq, cm) ((s->irq_state[irq].active & (cm)) != 0) -#define GIC_SET_MODEL(irq) s->irq_state[irq].model = 1 -#define GIC_CLEAR_MODEL(irq) s->irq_state[irq].model = 0 +#define GIC_SET_MODEL(irq) s->irq_state[irq].model = true +#define GIC_CLEAR_MODEL(irq) s->irq_state[irq].model = false #define GIC_TEST_MODEL(irq) s->irq_state[irq].model #define GIC_SET_LEVEL(irq, cm) s->irq_state[irq].level = (cm) #define GIC_CLEAR_LEVEL(irq, cm) s->irq_state[irq].level &= ~(cm) #define GIC_TEST_LEVEL(irq, cm) ((s->irq_state[irq].level & (cm)) != 0) -#define GIC_SET_TRIGGER(irq) s->irq_state[irq].trigger = 1 -#define GIC_CLEAR_TRIGGER(irq) s->irq_state[irq].trigger = 0 +#define GIC_SET_TRIGGER(irq) s->irq_state[irq].trigger = true +#define GIC_CLEAR_TRIGGER(irq) s->irq_state[irq].trigger = false #define GIC_TEST_TRIGGER(irq) s->irq_state[irq].trigger #define GIC_GET_PRIORITY(irq, cpu) (((irq) < GIC_INTERNAL) ? \ s->priority1[irq][cpu] : \ @@ -61,30 +61,30 @@ typedef struct gic_irq_state { /* The enable bits are only banked for per-cpu interrupts. */ - unsigned enabled:NCPU; - unsigned pending:NCPU; - unsigned active:NCPU; - unsigned level:NCPU; - unsigned model:1; /* 0 = N:N, 1 = 1:N */ - unsigned trigger:1; /* nonzero = edge triggered. */ + uint8_t enabled; + uint8_t pending; + uint8_t active; + uint8_t level; + bool model; /* 0 = N:N, 1 = 1:N */ + bool trigger; /* nonzero = edge triggered. */ } gic_irq_state; typedef struct GICState { SysBusDevice busdev; qemu_irq parent_irq[NCPU]; - int enabled; - int cpu_enabled[NCPU]; + bool enabled; + bool cpu_enabled[NCPU]; gic_irq_state irq_state[GIC_MAXIRQ]; - int irq_target[GIC_MAXIRQ]; - int priority1[GIC_INTERNAL][NCPU]; - int priority2[GIC_MAXIRQ - GIC_INTERNAL]; - int last_active[GIC_MAXIRQ][NCPU]; - - int priority_mask[NCPU]; - int running_irq[NCPU]; - int running_priority[NCPU]; - int current_pending[NCPU]; + uint8_t irq_target[GIC_MAXIRQ]; + uint8_t priority1[GIC_INTERNAL][NCPU]; + uint8_t priority2[GIC_MAXIRQ - GIC_INTERNAL]; + uint16_t last_active[GIC_MAXIRQ][NCPU]; + + uint16_t priority_mask[NCPU]; + uint16_t running_irq[NCPU]; + uint16_t running_priority[NCPU]; + uint16_t current_pending[NCPU]; uint32_t num_cpu; diff --git a/hw/armv7m_nvic.c b/hw/armv7m_nvic.c index d198cfd..b2a7fb7 100644 --- a/hw/armv7m_nvic.c +++ b/hw/armv7m_nvic.c @@ -458,10 +458,10 @@ static void armv7m_nvic_reset(DeviceState *dev) * as enabled by default, and with a priority mask which allows * all interrupts through. */ - s->gic.cpu_enabled[0] = 1; + s->gic.cpu_enabled[0] = false; s->gic.priority_mask[0] = 0x100; /* The NVIC as a whole is always enabled. */ - s->gic.enabled = 1; + s->gic.enabled = true; systick_reset(s); }