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[2001:8b0:1d0::1]) by mx.google.com with ESMTPS id fu4si1173446bkc.145.2013.02.22.11.12.28 (version=TLSv1 cipher=RC4-SHA bits=128/128); Fri, 22 Feb 2013 11:12:29 -0800 (PST) Received-SPF: neutral (google.com: 2001:8b0:1d0::1 is neither permitted nor denied by best guess record for domain of pm215@archaic.org.uk) client-ip=2001:8b0:1d0::1; Authentication-Results: mx.google.com; spf=neutral (google.com: 2001:8b0:1d0::1 is neither permitted nor denied by best guess record for domain of pm215@archaic.org.uk) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1U8xuz-0005m9-8T; Fri, 22 Feb 2013 19:04:25 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, kvm@vger.kernel.org, Marcelo Tosatti , kvmarm@lists.cs.columbia.edu, Blue Swirl , =?UTF-8?q?Andreas=20F=C3=A4rber?= , Gleb Natapov , Christoffer Dall , Paolo Bonzini Subject: [PATCH v6 5/9] hw/arm_gic: Add presave/postload hooks Date: Fri, 22 Feb 2013 19:04:21 +0000 Message-Id: <1361559865-22168-6-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1361559865-22168-1-git-send-email-peter.maydell@linaro.org> References: <1361559865-22168-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 X-Gm-Message-State: ALoCoQktN4DMFCx5W0hYIw1uJM4FVdA8ti7NMg50jsC6UDglm8uNVvD8iKm0U9b3fam+s1jY3Ams Add presave/postload hooks to the ARM GIC common base class. These will be used by the KVM in-kernel GIC subclass to sync state between kernel and userspace when migrating. Signed-off-by: Peter Maydell Reviewed-by: Andreas Färber Reviewed-by: Paolo Bonzini --- hw/arm_gic_common.c | 10 ++++++++++ hw/arm_gic_internal.h | 2 ++ 2 files changed, 12 insertions(+) diff --git a/hw/arm_gic_common.c b/hw/arm_gic_common.c index 40e8dd7..2947622 100644 --- a/hw/arm_gic_common.c +++ b/hw/arm_gic_common.c @@ -23,9 +23,14 @@ static void gic_save(QEMUFile *f, void *opaque) { GICState *s = (GICState *)opaque; + ARMGICCommonClass *c = ARM_GIC_COMMON_GET_CLASS(s); int i; int j; + if (c->pre_save) { + c->pre_save(s); + } + qemu_put_be32(f, s->enabled); for (i = 0; i < s->num_cpu; i++) { qemu_put_be32(f, s->cpu_enabled[i]); @@ -57,6 +62,7 @@ static void gic_save(QEMUFile *f, void *opaque) static int gic_load(QEMUFile *f, void *opaque, int version_id) { GICState *s = (GICState *)opaque; + ARMGICCommonClass *c = ARM_GIC_COMMON_GET_CLASS(s); int i; int j; @@ -91,6 +97,10 @@ static int gic_load(QEMUFile *f, void *opaque, int version_id) s->irq_state[i].trigger = qemu_get_byte(f); } + if (c->post_load) { + c->post_load(s); + } + return 0; } diff --git a/hw/arm_gic_internal.h b/hw/arm_gic_internal.h index 699352c..3640be0 100644 --- a/hw/arm_gic_internal.h +++ b/hw/arm_gic_internal.h @@ -118,6 +118,8 @@ void gic_init_irqs_and_distributor(GICState *s, int num_irq); typedef struct ARMGICCommonClass { SysBusDeviceClass parent_class; + void (*pre_save)(GICState *s); + void (*post_load)(GICState *s); } ARMGICCommonClass; #define TYPE_ARM_GIC "arm_gic"