From patchwork Fri Feb 22 18:10:00 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 15030 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 4A24C23F78 for ; Fri, 22 Feb 2013 18:10:17 +0000 (UTC) Received: from mail-ve0-f181.google.com (mail-ve0-f181.google.com [209.85.128.181]) by fiordland.canonical.com (Postfix) with ESMTP id E3BF0A18B66 for ; Fri, 22 Feb 2013 18:10:16 +0000 (UTC) Received: by mail-ve0-f181.google.com with SMTP id d10so784131vea.26 for ; Fri, 22 Feb 2013 10:10:16 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:x-forwarded-to:x-forwarded-for:delivered-to:x-received :received-spf:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references:x-gm-message-state; bh=vAK1mPBxCYYbNgOHmii0ZiXzJ9dcG0hg6XDftCc+PGw=; b=MGmiC/0J/0xI15UOZIfx+XmC9dwcD8ik4vHiiRJSfVnNdOibC9ZeJ1icHbTXqrSQ91 jWpqfiplDD19Wdn6wsk+vJzHrUT0Z5gInq2GEjE/yPQ7BMEPn/+47V63yasZXN/FerNW fiRMfC4SEhQeKqjECTj/0TK7Wq3EkFbedMtlfg/XRBxT4ltnlJ8haV1prIHFZeS6dz0C zXXa9jt+kltRvo5gYBwA6z1TIcqyto2PkhihsblLe85v6GpMuJdrUEhIKxYWPtYAHjMG 1PXtNhfxyVIMmuhAIEierRFXaZjAGjz0I3Tizsae6zpE1OBqe4iyEP84wJSS5RjyK7CU PMHA== X-Received: by 10.52.18.148 with SMTP id w20mr3430556vdd.8.1361556616343; Fri, 22 Feb 2013 10:10:16 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.58.145.101 with SMTP id st5csp101288veb; Fri, 22 Feb 2013 10:10:15 -0800 (PST) X-Received: by 10.194.108.101 with SMTP id hj5mr5411944wjb.6.1361556611984; Fri, 22 Feb 2013 10:10:11 -0800 (PST) Received: from mnementh.archaic.org.uk (1.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.d.1.0.0.b.8.0.1.0.0.2.ip6.arpa. [2001:8b0:1d0::1]) by mx.google.com with ESMTPS id ev2si1184867wid.58.2013.02.22.10.10.10 (version=TLSv1 cipher=RC4-SHA bits=128/128); Fri, 22 Feb 2013 10:10:11 -0800 (PST) Received-SPF: neutral (google.com: 2001:8b0:1d0::1 is neither permitted nor denied by best guess record for domain of pm215@archaic.org.uk) client-ip=2001:8b0:1d0::1; Authentication-Results: mx.google.com; spf=neutral (google.com: 2001:8b0:1d0::1 is neither permitted nor denied by best guess record for domain of pm215@archaic.org.uk) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1U8x4P-0005ii-UV; Fri, 22 Feb 2013 18:10:05 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Blue Swirl , =?UTF-8?q?Andreas=20F=C3=A4rber?= , Paul Brook , Anthony Liguori , Richard Henderson , Alexander Graf Subject: [PATCH 1/6] tcg: Document tcg_qemu_tb_exec() and provide constants for low bit uses Date: Fri, 22 Feb 2013 18:10:00 +0000 Message-Id: <1361556605-21963-2-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1361556605-21963-1-git-send-email-peter.maydell@linaro.org> References: <1361556605-21963-1-git-send-email-peter.maydell@linaro.org> X-Gm-Message-State: ALoCoQk0p3/k1KrXICssROdskatECsl/jXqJD4XLyaPtj/k+ONjdnU4sw5L1Ntvu4Fauc8TqnjpP Document tcg_qemu_tb_exec(). In particular, its return value is a combination of a pointer to the next translation block and some extra information in the low two bits. Provide some #defines for the values passed in these bits to improve code clarity. Signed-off-by: Peter Maydell --- cpu-exec.c | 9 +++++---- include/exec/gen-icount.h | 2 +- tcg/tcg.h | 44 +++++++++++++++++++++++++++++++++++++++++++- 3 files changed, 49 insertions(+), 6 deletions(-) diff --git a/cpu-exec.c b/cpu-exec.c index 9fcfe9e0..ea63e7d 100644 --- a/cpu-exec.c +++ b/cpu-exec.c @@ -72,7 +72,7 @@ static void cpu_exec_nocache(CPUArchState *env, int max_cycles, next_tb = tcg_qemu_tb_exec(env, tb->tc_ptr); cpu->current_tb = NULL; - if ((next_tb & 3) == 2) { + if ((next_tb & TB_EXIT_MASK) == TB_EXIT_ICOUNT_EXPIRED) { /* Restore PC. This may happen if async event occurs before the TB starts executing. */ cpu_pc_from_tb(env, tb); @@ -584,7 +584,8 @@ int cpu_exec(CPUArchState *env) spans two pages, we cannot safely do a direct jump. */ if (next_tb != 0 && tb->page_addr[1] == -1) { - tb_add_jump((TranslationBlock *)(next_tb & ~3), next_tb & 3, tb); + tb_add_jump((TranslationBlock *)(next_tb & ~TB_EXIT_MASK), + next_tb & TB_EXIT_MASK, tb); } spin_unlock(&tcg_ctx.tb_ctx.tb_lock); @@ -598,10 +599,10 @@ int cpu_exec(CPUArchState *env) tc_ptr = tb->tc_ptr; /* execute the generated code */ next_tb = tcg_qemu_tb_exec(env, tc_ptr); - if ((next_tb & 3) == 2) { + if ((next_tb & TB_EXIT_MASK) == TB_EXIT_ICOUNT_EXPIRED) { /* Instruction counter expired. */ int insns_left; - tb = (TranslationBlock *)(next_tb & ~3); + tb = (TranslationBlock *)(next_tb & ~TB_EXIT_MASK); /* Restore PC. */ cpu_pc_from_tb(env, tb); insns_left = env->icount_decr.u32; diff --git a/include/exec/gen-icount.h b/include/exec/gen-icount.h index 8043b3b..c858a73 100644 --- a/include/exec/gen-icount.h +++ b/include/exec/gen-icount.h @@ -32,7 +32,7 @@ static void gen_icount_end(TranslationBlock *tb, int num_insns) if (use_icount) { *icount_arg = num_insns; gen_set_label(icount_label); - tcg_gen_exit_tb((tcg_target_long)tb + 2); + tcg_gen_exit_tb((tcg_target_long)tb + TB_EXIT_ICOUNT_EXPIRED); } } diff --git a/tcg/tcg.h b/tcg/tcg.h index 51c8176..2ebde07 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -669,7 +669,49 @@ TCGv_i64 tcg_const_i64(int64_t val); TCGv_i32 tcg_const_local_i32(int32_t val); TCGv_i64 tcg_const_local_i64(int64_t val); -/* TCG targets may use a different definition of tcg_qemu_tb_exec. */ +/** + * tcg_qemu_tb_exec: + * @env: CPUArchState * for the CPU + * @tb_ptr: address of generated code for the TB to execute + * + * Start executing code from a given translation block. + * Where translation blocks have been linked, execution + * may proceed from the given TB into successive ones. + * Control eventually returns only when some action is needed + * from the top-level loop: either control must pass to a TB + * which has not yet been directly linked, or an asynchronous + * event such as an interrupt needs handling. + * + * The return value is a pointer to the next TB to execute + * (if known; otherwise zero). This pointer is assumed to be + * 4-aligned, and the bottom two bits are used to return further + * information: + * 0, 1: the link between this TB and the next is via the specified + * TB index (0 or 1). That is, we left the TB via (the equivalent + * of) "goto_tb ". The main loop uses this to determine + * how to link the TB just executed to the next. + * 2: we are using instruction counting code generation, and we + * did not start executing this TB because the instruction counter + * would hit zero midway through it. In this case the next-TB pointer + * returned is the TB we were about to execute, and the caller must + * arrange to execute the remaining count of instructions. + * + * If the bottom two bits indicate an exit-via-index then the CPU + * state is correctly synchronised and ready for execution of the next + * TB (and in particular the guest PC is the address to execute next). + * Otherwise, we gave up on execution of this TB before it started, and + * the caller must fix up the CPU state by calling cpu_pc_from_tb() + * with the next-TB pointer we return. + * + * Note that TCG targets may use a different definition of tcg_qemu_tb_exec + * to this default (which just calls the prologue.code emitted by + * tcg_target_qemu_prologue()). + */ +#define TB_EXIT_MASK 3 +#define TB_EXIT_IDX0 0 +#define TB_EXIT_IDX1 1 +#define TB_EXIT_ICOUNT_EXPIRED 2 + #if !defined(tcg_qemu_tb_exec) # define tcg_qemu_tb_exec(env, tb_ptr) \ ((tcg_target_ulong (*)(void *, void *))tcg_ctx.code_gen_prologue)(env, \