From patchwork Mon Feb 4 13:44:36 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 14536 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id CC3F023FEE for ; Mon, 4 Feb 2013 13:44:51 +0000 (UTC) Received: from mail-vb0-f54.google.com (mail-vb0-f54.google.com [209.85.212.54]) by fiordland.canonical.com (Postfix) with ESMTP id 75B60A18276 for ; Mon, 4 Feb 2013 13:44:51 +0000 (UTC) Received: by mail-vb0-f54.google.com with SMTP id l1so3898799vba.27 for ; Mon, 04 Feb 2013 05:44:51 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:x-forwarded-to:x-forwarded-for:delivered-to:x-received :received-spf:from:to:cc:subject:date:message-id:x-mailer :in-reply-to:references:x-gm-message-state; bh=81U68tPKBU0sCEsuW2ojuIZRo55WvLjQd4dEr01d1uo=; b=V83Y5qxtUuGthZEFSJH9xssFH1aOE7dAFVUArr5F3/bbTPIzEMZQ30MW4hsJbtZ2hP XSP7pRYX10hhtO/41kAexY6NFUI8qH5/qoytAOb16jNzY5KdmNZzo8Qpks5Fp1yIybT7 YQUXA3tnlogUU66YCw3K08CfRWgGwxu/n9jzeZaj4hzsz2CQbRw+I7iMHOLSM01sCyFa oUIO7+trE+L+Pj4GOJDwI+NXDIqFF9Mqo2kDL3ZTNg8pxaHI4FT3rwM25PhRfidxzSDo 86Yd1ArZwejtXyK9jk22PVtPDNtNIm2ghqL1M6oHLYLbgJMJ+WtqeqjF2vSu+bWT903o L/OQ== X-Received: by 10.52.21.146 with SMTP id v18mr19337563vde.79.1359985490855; Mon, 04 Feb 2013 05:44:50 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.58.252.8 with SMTP id zo8csp87660vec; Mon, 4 Feb 2013 05:44:50 -0800 (PST) X-Received: by 10.205.120.15 with SMTP id fw15mr5558040bkc.108.1359985488845; Mon, 04 Feb 2013 05:44:48 -0800 (PST) Received: from mnementh.archaic.org.uk (1.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.d.1.0.0.b.8.0.1.0.0.2.ip6.arpa. [2001:8b0:1d0::1]) by mx.google.com with ESMTPS id ia5si12094105bkc.118.2013.02.04.05.44.48 (version=TLSv1 cipher=RC4-SHA bits=128/128); Mon, 04 Feb 2013 05:44:48 -0800 (PST) Received-SPF: neutral (google.com: 2001:8b0:1d0::1 is neither permitted nor denied by best guess record for domain of pm215@archaic.org.uk) client-ip=2001:8b0:1d0::1; Authentication-Results: mx.google.com; spf=neutral (google.com: 2001:8b0:1d0::1 is neither permitted nor denied by best guess record for domain of pm215@archaic.org.uk) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1U2MLd-0007ed-K8; Mon, 04 Feb 2013 13:44:37 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Anthony Liguori Subject: [PATCH 10/10] hw/vexpress: Set reset values for daughterboard oscillators Date: Mon, 4 Feb 2013 13:44:36 +0000 Message-Id: <1359985476-29380-11-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1359985476-29380-1-git-send-email-peter.maydell@linaro.org> References: <1359985476-29380-1-git-send-email-peter.maydell@linaro.org> X-Gm-Message-State: ALoCoQm9hqY9c7ijBHxISWCEpepzZJXf6zwCpSnj1K0ShxPVESSoT5UZkCYok3cVgmBps4Wr01aZ Set the reset values for the VExpress daughterboard oscillators via the new sysctl properties. Signed-off-by: Peter Maydell --- hw/vexpress.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/hw/vexpress.c b/hw/vexpress.c index 8653200..547379a 100644 --- a/hw/vexpress.c +++ b/hw/vexpress.c @@ -156,6 +156,8 @@ struct VEDBoardInfo { uint32_t proc_id; uint32_t num_voltage_sensors; const uint32_t *voltages; + uint32_t num_clocks; + const uint32_t *clocks; DBoardInitFn *init; }; @@ -260,6 +262,13 @@ static const uint32_t a9_voltages[] = { 3300000, /* VCC3V3 : 3.3V : local board supply for misc external logic */ }; +/* Reset values for daughterboard oscillators (in Hz) */ +static const uint32_t a9_clocks[] = { + 45000000, /* AMBA AXI ACLK: 45MHz */ + 23750000, /* daughterboard CLCD clock: 23.75MHz */ + 66670000, /* Test chip reference clock: 66.67MHz */ +}; + static const VEDBoardInfo a9_daughterboard = { .motherboard_map = motherboard_legacy_map, .loader_start = 0x60000000, @@ -267,6 +276,8 @@ static const VEDBoardInfo a9_daughterboard = { .proc_id = 0x0c000191, .num_voltage_sensors = ARRAY_SIZE(a9_voltages), .voltages = a9_voltages, + .num_clocks = ARRAY_SIZE(a9_clocks), + .clocks = a9_clocks, .init = a9_daughterboard_init, }; @@ -358,6 +369,18 @@ static const uint32_t a15_voltages[] = { 900000, /* Vcore: 0.9V : CPU core voltage */ }; +static const uint32_t a15_clocks[] = { + 60000000, /* OSCCLK0: 60MHz : CPU_CLK reference */ + 0, /* OSCCLK1: reserved */ + 0, /* OSCCLK2: reserved */ + 0, /* OSCCLK3: reserved */ + 40000000, /* OSCCLK4: 40MHz : external AXI master clock */ + 23750000, /* OSCCLK5: 23.75MHz : HDLCD PLL reference */ + 50000000, /* OSCCLK6: 50MHz : static memory controller clock */ + 60000000, /* OSCCLK7: 60MHz : SYSCLK reference */ + 40000000, /* OSCCLK8: 40MHz : DDR2 PLL reference */ +}; + static const VEDBoardInfo a15_daughterboard = { .motherboard_map = motherboard_aseries_map, .loader_start = 0x80000000, @@ -365,6 +388,8 @@ static const VEDBoardInfo a15_daughterboard = { .proc_id = 0x14000237, .num_voltage_sensors = ARRAY_SIZE(a15_voltages), .voltages = a15_voltages, + .num_clocks = ARRAY_SIZE(a15_clocks), + .clocks = a15_clocks, .init = a15_daughterboard_init, }; @@ -400,6 +425,13 @@ static void vexpress_common_init(const VEDBoardInfo *daughterboard, qdev_prop_set_uint32(sysctl, propname, daughterboard->voltages[i]); g_free(propname); } + qdev_prop_set_uint32(sysctl, "len-db-clock", + daughterboard->num_clocks); + for (i = 0; i < daughterboard->num_clocks; i++) { + char *propname = g_strdup_printf("db-clock[%d]", i); + qdev_prop_set_uint32(sysctl, propname, daughterboard->clocks[i]); + g_free(propname); + } qdev_init_nofail(sysctl); sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, map[VE_SYSREGS]);