From patchwork Thu Nov 29 17:02:57 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 13292 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 8650324252 for ; Thu, 29 Nov 2012 17:03:03 +0000 (UTC) Received: from mail-ie0-f180.google.com (mail-ie0-f180.google.com [209.85.223.180]) by fiordland.canonical.com (Postfix) with ESMTP id 2C6BEA183E3 for ; Thu, 29 Nov 2012 17:03:03 +0000 (UTC) Received: by mail-ie0-f180.google.com with SMTP id c10so10378723ieb.11 for ; Thu, 29 Nov 2012 09:03:02 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=ugCgVcVx3lStH/QN7A6UhF3t+btepBKNw8JMF5JhXzw=; b=CmhBbqedXa2QhiR+RO9dtZuVwZjncVbyaGoUsvqKTuwpO44XRIS5+Fb70uAR0Xj2Jq W5pKFQ7hX91aRbbK0yITdnoWU8VHiMkuZWEOG72BVLukBEHQWr8PPnmd84RUVfzE3JKx VQxu6Jt4Xl7mO+RVUejS3yyq01DVFU+nD2XLKQvnwnU3PPuds6/BLuVR3G33v5+p50CZ qx2Rl47meoysHMHXanLUupFRjT0/ndb5/nl4+jG3z100dtEhCHySlNdU93uS2sAFLhkY wZHbL2sax7OdEIND6tsksTrkLDy6Sd7ho7CP9b8LEXCU/6nHVDIUvieGtlEkdzn584OQ QpUA== Received: by 10.50.161.169 with SMTP id xt9mr25706355igb.62.1354208582572; Thu, 29 Nov 2012 09:03:02 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.50.67.148 with SMTP id n20csp886772igt; Thu, 29 Nov 2012 09:03:01 -0800 (PST) Received: by 10.14.178.196 with SMTP id f44mr53380402eem.14.1354208581161; Thu, 29 Nov 2012 09:03:01 -0800 (PST) Received: from mnementh.archaic.org.uk (1.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.d.1.0.0.b.8.0.1.0.0.2.ip6.arpa. [2001:8b0:1d0::1]) by mx.google.com with ESMTPS id g47si4457389eep.3.2012.11.29.09.02.59 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 29 Nov 2012 09:03:01 -0800 (PST) Received-SPF: neutral (google.com: 2001:8b0:1d0::1 is neither permitted nor denied by best guess record for domain of pm215@archaic.org.uk) client-ip=2001:8b0:1d0::1; Authentication-Results: mx.google.com; spf=neutral (google.com: 2001:8b0:1d0::1 is neither permitted nor denied by best guess record for domain of pm215@archaic.org.uk) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1Te7Vp-0002Ke-8k; Thu, 29 Nov 2012 17:02:57 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, kvmarm@lists.cs.columbia.edu, Mark Langsdorf , Evgeny Voevodin , Maksim Kozlov , Igor Mitsyanko , Dmitry Solodkiy , Marc Zyngier Subject: [PATCH 3/3] hw/arm_gic_common: Correct GICC_PMR reset value for newer GICs Date: Thu, 29 Nov 2012 17:02:57 +0000 Message-Id: <1354208577-8935-4-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1354208577-8935-1-git-send-email-peter.maydell@linaro.org> References: <1354208577-8935-1-git-send-email-peter.maydell@linaro.org> X-Gm-Message-State: ALoCoQk3OJ2PVFCrc4iRMv6qv4IILDlpIiYIli1lCgdaWK22penWzNJXKvSnwsPEe2/3lYPahBZJ The GIC architecture specification for v1 and v2 GICs (as found on the Cortex-A9 and newer) states that the GICC_PMR reset value is zero; this differs from the 0xf0 reset value used on 11MPCore. The NVIC is different again in not having a CPU interface; since we share the GIC code we must force the priority mask field to allow through all interrupts. Signed-off-by: Peter Maydell Reviewed-by: Igor Mitsyanko --- hw/arm_gic_common.c | 6 +++++- hw/armv7m_nvic.c | 4 +++- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/hw/arm_gic_common.c b/hw/arm_gic_common.c index 8369309..73ae331 100644 --- a/hw/arm_gic_common.c +++ b/hw/arm_gic_common.c @@ -127,7 +127,11 @@ static void arm_gic_common_reset(DeviceState *dev) int i; memset(s->irq_state, 0, GIC_MAXIRQ * sizeof(gic_irq_state)); for (i = 0 ; i < s->num_cpu; i++) { - s->priority_mask[i] = 0xf0; + if (s->revision == REV_11MPCORE) { + s->priority_mask[i] = 0xf0; + } else { + s->priority_mask[i] = 0; + } s->current_pending[i] = 1023; s->running_irq[i] = 1023; s->running_priority[i] = 0x100; diff --git a/hw/armv7m_nvic.c b/hw/armv7m_nvic.c index f0a2e7b..4963678 100644 --- a/hw/armv7m_nvic.c +++ b/hw/armv7m_nvic.c @@ -455,9 +455,11 @@ static void armv7m_nvic_reset(DeviceState *dev) nc->parent_reset(dev); /* Common GIC reset resets to disabled; the NVIC doesn't have * per-CPU interfaces so mark our non-existent CPU interface - * as enabled by default. + * as enabled by default, and with a priority mask which allows + * all interrupts through. */ s->gic.cpu_enabled[0] = 1; + s->gic.priority_mask[0] = 0x100; /* The NVIC as a whole is always enabled. */ s->gic.enabled = 1; systick_reset(s);