From patchwork Thu Oct 25 12:57:44 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 12514 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id DE60323EFB for ; Thu, 25 Oct 2012 12:57:54 +0000 (UTC) Received: from mail-ie0-f180.google.com (mail-ie0-f180.google.com [209.85.223.180]) by fiordland.canonical.com (Postfix) with ESMTP id 90D5FA18FEF for ; Thu, 25 Oct 2012 12:57:54 +0000 (UTC) Received: by mail-ie0-f180.google.com with SMTP id e10so2060862iej.11 for ; Thu, 25 Oct 2012 05:57:54 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=ajduJ14yI+WNsiKuuhzDW2rN46FQpXyK8nJQx5a92JA=; b=iCpOqzP8uR1bJAuX9ZbJ8257qLXi86OEL/U6GIVk4rsbuRBhkUcRh1b+lFS/2oKuyi E+wZhRXfWk0cWINXZBX5+7weZDa+7PAMtv4MLgIbVadR8Xv4lybluYVGEP8CQPLPVkbo cfPaNBESd6AK8QFg1NZBg9VU2U1+dMzB50/oRyRilb3DF/1nXIZ5jdY74YVpJXNLWu40 sqyGwujpB8t/KkJEzFbPhzcsn4Kc/Me6nDzciodDp3rbWXoMywZ9ugncm7HsrSjmXLtF o5lKrXdi8lHtE9tHSuK4kIr7LuV1Q2SdollUPGHoJg555765hSvQYaGKKDHZZi2HPE90 0grQ== Received: by 10.50.140.97 with SMTP id rf1mr4225879igb.70.1351169874355; Thu, 25 Oct 2012 05:57:54 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.50.67.148 with SMTP id n20csp42921igt; Thu, 25 Oct 2012 05:57:51 -0700 (PDT) Received: by 10.204.150.210 with SMTP id z18mr5855391bkv.53.1351169871177; Thu, 25 Oct 2012 05:57:51 -0700 (PDT) Received: from mnementh.archaic.org.uk (1.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.d.1.0.0.b.8.0.1.0.0.2.ip6.arpa. [2001:8b0:1d0::1]) by mx.google.com with ESMTPS id hu13si27610197bkc.128.2012.10.25.05.57.50 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 25 Oct 2012 05:57:51 -0700 (PDT) Received-SPF: neutral (google.com: 2001:8b0:1d0::1 is neither permitted nor denied by best guess record for domain of pm215@archaic.org.uk) client-ip=2001:8b0:1d0::1; Authentication-Results: mx.google.com; spf=neutral (google.com: 2001:8b0:1d0::1 is neither permitted nor denied by best guess record for domain of pm215@archaic.org.uk) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1TRN0N-0001Qt-U8; Thu, 25 Oct 2012 13:57:47 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH 09/12] hw/armv7m_nvic: Use LOG_GUEST_ERROR and LOG_UNIMP Date: Thu, 25 Oct 2012 13:57:44 +0100 Message-Id: <1351169867-5466-10-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1351169867-5466-1-git-send-email-peter.maydell@linaro.org> References: <1351169867-5466-1-git-send-email-peter.maydell@linaro.org> X-Gm-Message-State: ALoCoQmaHEUmGQGqIw1r7GWMKbUlLjC2evQZX0TNcfIf8ngx27ujJjSL6QW8IRHEaNNLn6DqbGi3 Use LOG_GUEST_ERROR and LOG_UNIMP rather than hw_error() where appropriate. Signed-off-by: Peter Maydell --- hw/armv7m_nvic.c | 31 +++++++++++++++++++------------ 1 file changed, 19 insertions(+), 12 deletions(-) diff --git a/hw/armv7m_nvic.c b/hw/armv7m_nvic.c index 35c1aa6..ebf6282 100644 --- a/hw/armv7m_nvic.c +++ b/hw/armv7m_nvic.c @@ -243,7 +243,7 @@ static uint32_t nvic_readl(void *opaque, uint32_t offset) return val; case 0xd28: /* Configurable Fault Status. */ /* TODO: Implement Fault Status. */ - hw_error("Not implemented: Configurable Fault Status."); + qemu_log_mask(LOG_UNIMP, "Configurable Fault Status unimplemented\n"); return 0; case 0xd2c: /* Hard Fault Status. */ case 0xd30: /* Debug Fault Status. */ @@ -251,7 +251,8 @@ static uint32_t nvic_readl(void *opaque, uint32_t offset) case 0xd38: /* Bus Fault Address. */ case 0xd3c: /* Aux Fault Status. */ /* TODO: Implement fault status registers. */ - goto bad_reg; + qemu_log_mask(LOG_UNIMP, "Fault status registers unimplemented\n"); + return 0; case 0xd40: /* PFR0. */ return 0x00000030; case 0xd44: /* PRF1. */ @@ -280,8 +281,8 @@ static uint32_t nvic_readl(void *opaque, uint32_t offset) return 0x01310102; /* TODO: Implement debug registers. */ default: - bad_reg: - hw_error("NVIC: Bad read offset 0x%x\n", offset); + qemu_log_mask(LOG_GUEST_ERROR, "NVIC: Bad read offset 0x%x\n", offset); + return 0; } } @@ -345,17 +346,18 @@ static void nvic_writel(void *opaque, uint32_t offset, uint32_t value) case 0xd0c: /* Application Interrupt/Reset Control. */ if ((value >> 16) == 0x05fa) { if (value & 2) { - hw_error("VECTCLRACTIVE not implemented"); + qemu_log_mask(LOG_UNIMP, "VECTCLRACTIVE unimplemented\n"); } if (value & 5) { - hw_error("System reset"); + qemu_log_mask(LOG_UNIMP, "AIRCR system reset unimplemented\n"); } } break; case 0xd10: /* System Control. */ case 0xd14: /* Configuration Control. */ /* TODO: Implement control registers. */ - goto bad_reg; + qemu_log_mask(LOG_UNIMP, "NVIC: SCR and CCR unimplemented\n"); + break; case 0xd18: case 0xd1c: case 0xd20: /* System Handler Priority. */ { int irq; @@ -380,15 +382,17 @@ static void nvic_writel(void *opaque, uint32_t offset, uint32_t value) case 0xd34: /* Mem Manage Address. */ case 0xd38: /* Bus Fault Address. */ case 0xd3c: /* Aux Fault Status. */ - goto bad_reg; + qemu_log_mask(LOG_UNIMP, + "NVIC: fault status registers unimplemented\n"); + break; case 0xf00: /* Software Triggered Interrupt Register */ if ((value & 0x1ff) < s->num_irq) { gic_set_pending_private(&s->gic, 0, value & 0x1ff); } break; default: - bad_reg: - hw_error("NVIC: Bad write offset 0x%x\n", offset); + qemu_log_mask(LOG_GUEST_ERROR, + "NVIC: Bad write offset 0x%x\n", offset); } } @@ -409,7 +413,9 @@ static uint64_t nvic_sysreg_read(void *opaque, hwaddr addr, if (size == 4) { return nvic_readl(opaque, offset); } - hw_error("NVIC: Bad read of size %d at offset 0x%x\n", size, offset); + qemu_log_mask(LOG_GUEST_ERROR, + "NVIC: Bad read of size %d at offset 0x%x\n", size, offset); + return 0; } static void nvic_sysreg_write(void *opaque, hwaddr addr, @@ -420,7 +426,8 @@ static void nvic_sysreg_write(void *opaque, hwaddr addr, nvic_writel(opaque, offset, value); return; } - hw_error("NVIC: Bad write of size %d at offset 0x%x\n", size, offset); + qemu_log_mask(LOG_GUEST_ERROR, + "NVIC: Bad write of size %d at offset 0x%x\n", size, offset); } static const MemoryRegionOps nvic_sysreg_ops = {