From patchwork Tue Oct 23 10:50:24 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 12431 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 6D69823E29 for ; Tue, 23 Oct 2012 10:50:37 +0000 (UTC) Received: from mail-ie0-f180.google.com (mail-ie0-f180.google.com [209.85.223.180]) by fiordland.canonical.com (Postfix) with ESMTP id 016F1A18877 for ; Tue, 23 Oct 2012 10:50:36 +0000 (UTC) Received: by mail-ie0-f180.google.com with SMTP id e10so4853864iej.11 for ; Tue, 23 Oct 2012 03:50:36 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:in-reply-to:references :mime-version:content-type:content-transfer-encoding :x-gm-message-state; bh=ZdLKVVv2nnvjqZcDfwmUjSac/T+K3uIk9NKsmjrC9+M=; b=fYovcpBC7OW5iuLwHJV3pIAbwM8S1MIkRb6Da3hvKk9ZY6BcKJNJ2S9i+KeM+XWUob wTb6RjQ4b5ZB2Eouo5I+7gBQcp0wccrPdIvoK0DuP++VZDZZtdAmU0NauErsQ9/7zsC5 p4ge4T8vtuINLvGSS5zal94JQQWk9LR7ilcj8aQcRutkuUtEhZcnk8b+WbFQZR5dqMTs i+xuYKGABQL39NF7vv2NMDuhdXayb8O5FP4VZ9aJc7+6uB6DuiwynZLM0XVIFhdXDWPb JKwloxVBOLtHZ6HXNDQj81OZO8Mg/Zmm+y9xjsIcSdXYyY1qiTVO9dMglTarxFK7WiJ6 auOw== Received: by 10.50.194.169 with SMTP id hx9mr12210810igc.70.1350989436215; Tue, 23 Oct 2012 03:50:36 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.50.67.148 with SMTP id n20csp403695igt; Tue, 23 Oct 2012 03:50:35 -0700 (PDT) Received: by 10.216.207.103 with SMTP id m81mr6968733weo.190.1350989434276; Tue, 23 Oct 2012 03:50:34 -0700 (PDT) Received: from mnementh.archaic.org.uk (1.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.d.1.0.0.b.8.0.1.0.0.2.ip6.arpa. [2001:8b0:1d0::1]) by mx.google.com with ESMTPS id e47si12145685weq.155.2012.10.23.03.50.33 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 23 Oct 2012 03:50:34 -0700 (PDT) Received-SPF: neutral (google.com: 2001:8b0:1d0::1 is neither permitted nor denied by best guess record for domain of pm215@archaic.org.uk) client-ip=2001:8b0:1d0::1; Authentication-Results: mx.google.com; spf=neutral (google.com: 2001:8b0:1d0::1 is neither permitted nor denied by best guess record for domain of pm215@archaic.org.uk) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1TQc44-0000Fk-Eu; Tue, 23 Oct 2012 11:50:28 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu, patches@linaro.org, Blue Swirl , =?UTF-8?q?Andreas=20F=C3=A4rber?= , Avi Kivity , Marcelo Tosatti Subject: [RFC v3 4/8] hw/arm_gic: Add presave/postload hooks Date: Tue, 23 Oct 2012 11:50:24 +0100 Message-Id: <1350989428-941-5-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1350989428-941-1-git-send-email-peter.maydell@linaro.org> References: <1350989428-941-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 X-Gm-Message-State: ALoCoQlSsjILt5nKCUuPbN3pN88Pa8ggbIsKC/mCedTcpEEUWvuLCzwTl8bguP+Sb7CSXfUUZc4N Add presave/postload hooks to the ARM GIC common base class. These will be used by the KVM in-kernel GIC subclass to sync state between kernel and userspace when migrating. Signed-off-by: Peter Maydell Reviewed-by: Andreas Färber --- hw/arm_gic_common.c | 10 ++++++++++ hw/arm_gic_internal.h | 2 ++ 2 files changed, 12 insertions(+) diff --git a/hw/arm_gic_common.c b/hw/arm_gic_common.c index 8369309..961b44c 100644 --- a/hw/arm_gic_common.c +++ b/hw/arm_gic_common.c @@ -23,9 +23,14 @@ static void gic_save(QEMUFile *f, void *opaque) { GICState *s = (GICState *)opaque; + ARMGICCommonClass *c = ARM_GIC_COMMON_GET_CLASS(s); int i; int j; + if (c->pre_save) { + c->pre_save(s); + } + qemu_put_be32(f, s->enabled); for (i = 0; i < s->num_cpu; i++) { qemu_put_be32(f, s->cpu_enabled[i]); @@ -57,6 +62,7 @@ static void gic_save(QEMUFile *f, void *opaque) static int gic_load(QEMUFile *f, void *opaque, int version_id) { GICState *s = (GICState *)opaque; + ARMGICCommonClass *c = ARM_GIC_COMMON_GET_CLASS(s); int i; int j; @@ -91,6 +97,10 @@ static int gic_load(QEMUFile *f, void *opaque, int version_id) s->irq_state[i].trigger = qemu_get_byte(f); } + if (c->post_load) { + c->post_load(s); + } + return 0; } diff --git a/hw/arm_gic_internal.h b/hw/arm_gic_internal.h index 699352c..3640be0 100644 --- a/hw/arm_gic_internal.h +++ b/hw/arm_gic_internal.h @@ -118,6 +118,8 @@ void gic_init_irqs_and_distributor(GICState *s, int num_irq); typedef struct ARMGICCommonClass { SysBusDeviceClass parent_class; + void (*pre_save)(GICState *s); + void (*post_load)(GICState *s); } ARMGICCommonClass; #define TYPE_ARM_GIC "arm_gic"