From patchwork Sun Oct 14 13:11:16 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 12211 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 3141D23F9C for ; Sun, 14 Oct 2012 13:11:22 +0000 (UTC) Received: from mail-ia0-f180.google.com (mail-ia0-f180.google.com [209.85.210.180]) by fiordland.canonical.com (Postfix) with ESMTP id CF44DA18C46 for ; Sun, 14 Oct 2012 13:11:21 +0000 (UTC) Received: by mail-ia0-f180.google.com with SMTP id f6so3022268iag.11 for ; Sun, 14 Oct 2012 06:11:21 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=kjbGvcpa1lRbFgvUq9MrQESk0ewL7fasCrywBFRqQMs=; b=pLMSrhXmQAtjzi4smgvts0v/RHy2IdaioOJ8p8iH7FCuUGUIbVpeJDVPshB6m8VGyu yrhsgJAnY7Jh3xMJklS1Se48BMeFFPB15EP0Wx+0F69Jy9OBG8jAG2tOTHIjenEzjvHe IMu5MU1kggLY22zR5ZWhf+IPt2XXnHZ56ohsMjapWkJnsP2S+wST8b2HE/h9+9Hb2CuC uqsGXR207JONXbtCw2w/2xjQMSFVnO5K/wOt2bbt0Bui+xQNZemyXaTR8q4CBbDW9nF2 cJen9t1QGjPmYyU4zQC1eVx2a+5FOqp9bKL6dsmus2pBOppmJUVpqBZPouRZyTR6Mt4B 2PPA== Received: by 10.50.91.195 with SMTP id cg3mr6366126igb.57.1350220281082; Sun, 14 Oct 2012 06:11:21 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.50.67.148 with SMTP id n20csp450959igt; Sun, 14 Oct 2012 06:11:20 -0700 (PDT) Received: by 10.205.130.148 with SMTP id hm20mr2458438bkc.71.1350220279554; Sun, 14 Oct 2012 06:11:19 -0700 (PDT) Received: from mnementh.archaic.org.uk (1.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.d.1.0.0.b.8.0.1.0.0.2.ip6.arpa. [2001:8b0:1d0::1]) by mx.google.com with ESMTPS id fy18si20585149bkc.137.2012.10.14.06.11.18 (version=TLSv1/SSLv3 cipher=OTHER); Sun, 14 Oct 2012 06:11:19 -0700 (PDT) Received-SPF: neutral (google.com: 2001:8b0:1d0::1 is neither permitted nor denied by best guess record for domain of pm215@archaic.org.uk) client-ip=2001:8b0:1d0::1; Authentication-Results: mx.google.com; spf=neutral (google.com: 2001:8b0:1d0::1 is neither permitted nor denied by best guess record for domain of pm215@archaic.org.uk) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1TNNyO-0004GM-DD; Sun, 14 Oct 2012 14:11:16 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Blue Swirl Subject: [PATCH 7/7] hw/pl031: Use LOG_GUEST_ERROR Date: Sun, 14 Oct 2012 14:11:16 +0100 Message-Id: <1350220276-16349-8-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1350220276-16349-1-git-send-email-peter.maydell@linaro.org> References: <1350220276-16349-1-git-send-email-peter.maydell@linaro.org> X-Gm-Message-State: ALoCoQmBbWKxIsdqLPafa1jw6BuKHf5/9quxeXSmW6/mKa8vkjEfvNUQ0iMzOo8JLD7yWc3h0eDF Use LOG_GUEST_ERROR rather than hw_error or direct fprintf. Signed-off-by: Peter Maydell --- hw/pl031.c | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/hw/pl031.c b/hw/pl031.c index 9602664..a718d2e 100644 --- a/hw/pl031.c +++ b/hw/pl031.c @@ -14,6 +14,7 @@ #include "sysbus.h" #include "qemu-timer.h" #include "sysemu.h" +#include "qemu-log.h" //#define DEBUG_PL031 @@ -120,11 +121,13 @@ static uint64_t pl031_read(void *opaque, target_phys_addr_t offset, case RTC_MIS: return s->is & s->im; case RTC_ICR: - fprintf(stderr, "qemu: pl031_read: Unexpected offset 0x%x\n", - (int)offset); + qemu_log_mask(LOG_GUEST_ERROR, + "pl031: read of write-only register at offset 0x%x\n", + (int)offset); break; default: - hw_error("pl031_read: Bad offset 0x%x\n", (int)offset); + qemu_log_mask(LOG_GUEST_ERROR, + "pl031_read: Bad offset 0x%x\n", (int)offset); break; } @@ -167,12 +170,14 @@ static void pl031_write(void * opaque, target_phys_addr_t offset, case RTC_DR: case RTC_MIS: case RTC_RIS: - fprintf(stderr, "qemu: pl031_write: Unexpected offset 0x%x\n", - (int)offset); + qemu_log_mask(LOG_GUEST_ERROR, + "pl031: write to read-only register at offset 0x%x\n", + (int)offset); break; default: - hw_error("pl031_write: Bad offset 0x%x\n", (int)offset); + qemu_log_mask(LOG_GUEST_ERROR, + "pl031_write: Bad offset 0x%x\n", (int)offset); break; } }