From patchwork Wed Oct 10 17:49:05 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 12155 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 7135E23DE1 for ; Wed, 10 Oct 2012 17:49:13 +0000 (UTC) Received: from mail-ie0-f180.google.com (mail-ie0-f180.google.com [209.85.223.180]) by fiordland.canonical.com (Postfix) with ESMTP id 05488A1801C for ; Wed, 10 Oct 2012 17:49:12 +0000 (UTC) Received: by mail-ie0-f180.google.com with SMTP id e10so1389234iej.11 for ; Wed, 10 Oct 2012 10:49:12 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:x-gm-message-state; bh=8w5PzgQzevLfY0qmi1E4hTm/eq3/4EI1hZCqeG+Uu8g=; b=IKEuTw+nBVh93FgE6qdskavy27AdH0+yqgtUB1Y1sGbM6XJJ1/XJZLTRFpMvdAVftx B4KbTe4FmJ3Fsqz4FvxEUg52BoYhufrbdZU7wK5xQb5b9roenzvzApbEDMVnHzvi3uza PhRbmvg65TNcYxul/sEH5K1+9LYvsSY4+DW18+aZGMdqOG41LQMOhjzfc5Y1D3PdyTCZ GstdHGeYo+QmSFTaRBvdMblJ5oBySmSQ6I2lc4MpfIu0Dfaqwcw1Jt1ZyAyjnG6v/YG2 2lsUP/e08BL8QXLSdGZlL5+h+R2SaUg8l2RCmRTDTNg0QSr4atURqSk79igYwSeYPZYo uhzw== Received: by 10.50.236.72 with SMTP id us8mr6066408igc.70.1349891351043; Wed, 10 Oct 2012 10:49:11 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.50.67.148 with SMTP id n20csp261773igt; Wed, 10 Oct 2012 10:49:09 -0700 (PDT) Received: by 10.216.200.150 with SMTP id z22mr3444495wen.97.1349891348817; Wed, 10 Oct 2012 10:49:08 -0700 (PDT) Received: from mnementh.archaic.org.uk (1.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.d.1.0.0.b.8.0.1.0.0.2.ip6.arpa. [2001:8b0:1d0::1]) by mx.google.com with ESMTPS id y49si2311080wen.33.2012.10.10.10.49.08 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 10 Oct 2012 10:49:08 -0700 (PDT) Received-SPF: neutral (google.com: 2001:8b0:1d0::1 is neither permitted nor denied by best guess record for domain of pm215@archaic.org.uk) client-ip=2001:8b0:1d0::1; Authentication-Results: mx.google.com; spf=neutral (google.com: 2001:8b0:1d0::1 is neither permitted nor denied by best guess record for domain of pm215@archaic.org.uk) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1TM0P3-0002G3-Oh; Wed, 10 Oct 2012 18:49:05 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, =?UTF-8?q?Andreas=20F=C3=A4rber?= Subject: [PATCH] arm_gic: Rename gic_state to GICState Date: Wed, 10 Oct 2012 18:49:05 +0100 Message-Id: <1349891345-8656-1-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 X-Gm-Message-State: ALoCoQlmXasSKIRMmIzHJbVg1gyxEqcALnuAGmRoHVA18fHdCJu2OSQVMO/8vaU1thzYAd/JEY0j Rename the gic_state struct to match QEMU's coding style conventions for structure names, since the impending KVM-for-ARM patches will create another subclass of it. This patch was created using: sed -i 's/gic_state/GICState/g' hw/arm_gic.c hw/arm_gic_common.c \ hw/arm_gic_internal.h hw/armv7m_nvic.c Signed-off-by: Peter Maydell Acked-by: Andreas Färber --- As suggested by Andreas... hw/arm_gic.c | 44 ++++++++++++++++++++++---------------------- hw/arm_gic_common.c | 16 ++++++++-------- hw/arm_gic_internal.h | 20 ++++++++++---------- hw/armv7m_nvic.c | 6 +++--- 4 files changed, 43 insertions(+), 43 deletions(-) diff --git a/hw/arm_gic.c b/hw/arm_gic.c index 55871fa..3ce989a 100644 --- a/hw/arm_gic.c +++ b/hw/arm_gic.c @@ -36,7 +36,7 @@ static const uint8_t gic_id[] = { #define NUM_CPU(s) ((s)->num_cpu) -static inline int gic_get_current_cpu(gic_state *s) +static inline int gic_get_current_cpu(GICState *s) { if (s->num_cpu > 1) { return cpu_single_env->cpu_index; @@ -46,7 +46,7 @@ static inline int gic_get_current_cpu(gic_state *s) /* TODO: Many places that call this routine could be optimized. */ /* Update interrupt status after enabled or pending bits have been changed. */ -void gic_update(gic_state *s) +void gic_update(GICState *s) { int best_irq; int best_prio; @@ -84,7 +84,7 @@ void gic_update(gic_state *s) } } -void gic_set_pending_private(gic_state *s, int cpu, int irq) +void gic_set_pending_private(GICState *s, int cpu, int irq) { int cm = 1 << cpu; @@ -105,7 +105,7 @@ static void gic_set_irq(void *opaque, int irq, int level) * [N+32..N+63] : PPI (internal interrupts for CPU 1 * ... */ - gic_state *s = (gic_state *)opaque; + GICState *s = (GICState *)opaque; int cm, target; if (irq < (s->num_irq - GIC_INTERNAL)) { /* The first external input line is internal interrupt 32. */ @@ -137,7 +137,7 @@ static void gic_set_irq(void *opaque, int irq, int level) gic_update(s); } -static void gic_set_running_irq(gic_state *s, int cpu, int irq) +static void gic_set_running_irq(GICState *s, int cpu, int irq) { s->running_irq[cpu] = irq; if (irq == 1023) { @@ -148,7 +148,7 @@ static void gic_set_running_irq(gic_state *s, int cpu, int irq) gic_update(s); } -uint32_t gic_acknowledge_irq(gic_state *s, int cpu) +uint32_t gic_acknowledge_irq(GICState *s, int cpu) { int new_irq; int cm = 1 << cpu; @@ -167,7 +167,7 @@ uint32_t gic_acknowledge_irq(gic_state *s, int cpu) return new_irq; } -void gic_complete_irq(gic_state *s, int cpu, int irq) +void gic_complete_irq(GICState *s, int cpu, int irq) { int update = 0; int cm = 1 << cpu; @@ -214,7 +214,7 @@ void gic_complete_irq(gic_state *s, int cpu, int irq) static uint32_t gic_dist_readb(void *opaque, target_phys_addr_t offset) { - gic_state *s = (gic_state *)opaque; + GICState *s = (GICState *)opaque; uint32_t res; int irq; int i; @@ -347,7 +347,7 @@ static uint32_t gic_dist_readl(void *opaque, target_phys_addr_t offset) static void gic_dist_writeb(void *opaque, target_phys_addr_t offset, uint32_t value) { - gic_state *s = (gic_state *)opaque; + GICState *s = (GICState *)opaque; int irq; int i; int cpu; @@ -500,7 +500,7 @@ static void gic_dist_writew(void *opaque, target_phys_addr_t offset, static void gic_dist_writel(void *opaque, target_phys_addr_t offset, uint32_t value) { - gic_state *s = (gic_state *)opaque; + GICState *s = (GICState *)opaque; if (offset == 0xf00) { int cpu; int irq; @@ -539,7 +539,7 @@ static const MemoryRegionOps gic_dist_ops = { .endianness = DEVICE_NATIVE_ENDIAN, }; -static uint32_t gic_cpu_read(gic_state *s, int cpu, int offset) +static uint32_t gic_cpu_read(GICState *s, int cpu, int offset) { switch (offset) { case 0x00: /* Control */ @@ -561,7 +561,7 @@ static uint32_t gic_cpu_read(gic_state *s, int cpu, int offset) } } -static void gic_cpu_write(gic_state *s, int cpu, int offset, uint32_t value) +static void gic_cpu_write(GICState *s, int cpu, int offset, uint32_t value) { switch (offset) { case 0x00: /* Control */ @@ -587,25 +587,25 @@ static void gic_cpu_write(gic_state *s, int cpu, int offset, uint32_t value) static uint64_t gic_thiscpu_read(void *opaque, target_phys_addr_t addr, unsigned size) { - gic_state *s = (gic_state *)opaque; + GICState *s = (GICState *)opaque; return gic_cpu_read(s, gic_get_current_cpu(s), addr); } static void gic_thiscpu_write(void *opaque, target_phys_addr_t addr, uint64_t value, unsigned size) { - gic_state *s = (gic_state *)opaque; + GICState *s = (GICState *)opaque; gic_cpu_write(s, gic_get_current_cpu(s), addr, value); } /* Wrappers to read/write the GIC CPU interface for a specific CPU. - * These just decode the opaque pointer into gic_state* + cpu id. + * These just decode the opaque pointer into GICState* + cpu id. */ static uint64_t gic_do_cpu_read(void *opaque, target_phys_addr_t addr, unsigned size) { - gic_state **backref = (gic_state **)opaque; - gic_state *s = *backref; + GICState **backref = (GICState **)opaque; + GICState *s = *backref; int id = (backref - s->backref); return gic_cpu_read(s, id, addr); } @@ -613,8 +613,8 @@ static uint64_t gic_do_cpu_read(void *opaque, target_phys_addr_t addr, static void gic_do_cpu_write(void *opaque, target_phys_addr_t addr, uint64_t value, unsigned size) { - gic_state **backref = (gic_state **)opaque; - gic_state *s = *backref; + GICState **backref = (GICState **)opaque; + GICState *s = *backref; int id = (backref - s->backref); gic_cpu_write(s, id, addr, value); } @@ -631,7 +631,7 @@ static const MemoryRegionOps gic_cpu_ops = { .endianness = DEVICE_NATIVE_ENDIAN, }; -void gic_init_irqs_and_distributor(gic_state *s, int num_irq) +void gic_init_irqs_and_distributor(GICState *s, int num_irq) { int i; @@ -657,7 +657,7 @@ static int arm_gic_init(SysBusDevice *dev) { /* Device instance init function for the GIC sysbus device */ int i; - gic_state *s = FROM_SYSBUS(gic_state, dev); + GICState *s = FROM_SYSBUS(GICState, dev); ARMGICClass *agc = ARM_GIC_GET_CLASS(s); agc->parent_init(dev); @@ -701,7 +701,7 @@ static void arm_gic_class_init(ObjectClass *klass, void *data) static TypeInfo arm_gic_info = { .name = TYPE_ARM_GIC, .parent = TYPE_ARM_GIC_COMMON, - .instance_size = sizeof(gic_state), + .instance_size = sizeof(GICState), .class_init = arm_gic_class_init, .class_size = sizeof(ARMGICClass), }; diff --git a/hw/arm_gic_common.c b/hw/arm_gic_common.c index 360e782..8369309 100644 --- a/hw/arm_gic_common.c +++ b/hw/arm_gic_common.c @@ -22,7 +22,7 @@ static void gic_save(QEMUFile *f, void *opaque) { - gic_state *s = (gic_state *)opaque; + GICState *s = (GICState *)opaque; int i; int j; @@ -56,7 +56,7 @@ static void gic_save(QEMUFile *f, void *opaque) static int gic_load(QEMUFile *f, void *opaque, int version_id) { - gic_state *s = (gic_state *)opaque; + GICState *s = (GICState *)opaque; int i; int j; @@ -96,7 +96,7 @@ static int gic_load(QEMUFile *f, void *opaque, int version_id) static int arm_gic_common_init(SysBusDevice *dev) { - gic_state *s = FROM_SYSBUS(gic_state, dev); + GICState *s = FROM_SYSBUS(GICState, dev); int num_irq = s->num_irq; if (s->num_cpu > NCPU) { @@ -123,7 +123,7 @@ static int arm_gic_common_init(SysBusDevice *dev) static void arm_gic_common_reset(DeviceState *dev) { - gic_state *s = FROM_SYSBUS(gic_state, sysbus_from_qdev(dev)); + GICState *s = FROM_SYSBUS(GICState, sysbus_from_qdev(dev)); int i; memset(s->irq_state, 0, GIC_MAXIRQ * sizeof(gic_irq_state)); for (i = 0 ; i < s->num_cpu; i++) { @@ -147,13 +147,13 @@ static void arm_gic_common_reset(DeviceState *dev) } static Property arm_gic_common_properties[] = { - DEFINE_PROP_UINT32("num-cpu", gic_state, num_cpu, 1), - DEFINE_PROP_UINT32("num-irq", gic_state, num_irq, 32), + DEFINE_PROP_UINT32("num-cpu", GICState, num_cpu, 1), + DEFINE_PROP_UINT32("num-irq", GICState, num_irq, 32), /* Revision can be 1 or 2 for GIC architecture specification * versions 1 or 2, or 0 to indicate the legacy 11MPCore GIC. * (Internally, 0xffffffff also indicates "not a GIC but an NVIC".) */ - DEFINE_PROP_UINT32("revision", gic_state, revision, 1), + DEFINE_PROP_UINT32("revision", GICState, revision, 1), DEFINE_PROP_END_OF_LIST(), }; @@ -170,7 +170,7 @@ static void arm_gic_common_class_init(ObjectClass *klass, void *data) static TypeInfo arm_gic_common_type = { .name = TYPE_ARM_GIC_COMMON, .parent = TYPE_SYS_BUS_DEVICE, - .instance_size = sizeof(gic_state), + .instance_size = sizeof(GICState), .class_size = sizeof(ARMGICCommonClass), .class_init = arm_gic_common_class_init, .abstract = true, diff --git a/hw/arm_gic_internal.h b/hw/arm_gic_internal.h index db4fad5..699352c 100644 --- a/hw/arm_gic_internal.h +++ b/hw/arm_gic_internal.h @@ -69,7 +69,7 @@ typedef struct gic_irq_state { unsigned trigger:1; /* nonzero = edge triggered. */ } gic_irq_state; -typedef struct gic_state { +typedef struct GICState { SysBusDevice busdev; qemu_irq parent_irq[NCPU]; int enabled; @@ -92,25 +92,25 @@ typedef struct gic_state { /* This is just so we can have an opaque pointer which identifies * both this GIC and which CPU interface we should be accessing. */ - struct gic_state *backref[NCPU]; + struct GICState *backref[NCPU]; MemoryRegion cpuiomem[NCPU+1]; /* CPU interfaces */ uint32_t num_irq; uint32_t revision; -} gic_state; +} GICState; /* The special cases for the revision property: */ #define REV_11MPCORE 0 #define REV_NVIC 0xffffffff -void gic_set_pending_private(gic_state *s, int cpu, int irq); -uint32_t gic_acknowledge_irq(gic_state *s, int cpu); -void gic_complete_irq(gic_state *s, int cpu, int irq); -void gic_update(gic_state *s); -void gic_init_irqs_and_distributor(gic_state *s, int num_irq); +void gic_set_pending_private(GICState *s, int cpu, int irq); +uint32_t gic_acknowledge_irq(GICState *s, int cpu); +void gic_complete_irq(GICState *s, int cpu, int irq); +void gic_update(GICState *s); +void gic_init_irqs_and_distributor(GICState *s, int num_irq); #define TYPE_ARM_GIC_COMMON "arm_gic_common" #define ARM_GIC_COMMON(obj) \ - OBJECT_CHECK(gic_state, (obj), TYPE_ARM_GIC_COMMON) + OBJECT_CHECK(GICState, (obj), TYPE_ARM_GIC_COMMON) #define ARM_GIC_COMMON_CLASS(klass) \ OBJECT_CLASS_CHECK(ARMGICCommonClass, (klass), TYPE_ARM_GIC_COMMON) #define ARM_GIC_COMMON_GET_CLASS(obj) \ @@ -122,7 +122,7 @@ typedef struct ARMGICCommonClass { #define TYPE_ARM_GIC "arm_gic" #define ARM_GIC(obj) \ - OBJECT_CHECK(gic_state, (obj), TYPE_ARM_GIC) + OBJECT_CHECK(GICState, (obj), TYPE_ARM_GIC) #define ARM_GIC_CLASS(klass) \ OBJECT_CLASS_CHECK(ARMGICClass, (klass), TYPE_ARM_GIC) #define ARM_GIC_GET_CLASS(obj) \ diff --git a/hw/armv7m_nvic.c b/hw/armv7m_nvic.c index 5c09116..c449e08 100644 --- a/hw/armv7m_nvic.c +++ b/hw/armv7m_nvic.c @@ -17,7 +17,7 @@ #include "arm_gic_internal.h" typedef struct { - gic_state gic; + GICState gic; struct { uint32_t control; uint32_t reload; @@ -505,9 +505,9 @@ static void armv7m_nvic_instance_init(Object *obj) * than our superclass. This function runs after qdev init * has set the defaults from the Property array and before * any user-specified property setting, so just modify the - * value in the gic_state struct. + * value in the GICState struct. */ - gic_state *s = ARM_GIC_COMMON(obj); + GICState *s = ARM_GIC_COMMON(obj); /* The ARM v7m may have anything from 0 to 496 external interrupt * IRQ lines. We default to 64. Other boards may differ and should * set the num-irq property appropriately.