From patchwork Wed Oct 10 15:07:38 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 12136 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 8CA8123E01 for ; Wed, 10 Oct 2012 15:07:48 +0000 (UTC) Received: from mail-ia0-f180.google.com (mail-ia0-f180.google.com [209.85.210.180]) by fiordland.canonical.com (Postfix) with ESMTP id F3D9BA190C9 for ; Wed, 10 Oct 2012 15:07:47 +0000 (UTC) Received: by mail-ia0-f180.google.com with SMTP id f6so431027iag.11 for ; Wed, 10 Oct 2012 08:07:47 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=itxA2fPnSNmJZ1FBokGhoasR9AIQUe2Bb7nOsjdbVMU=; b=Kalt6aGaxXknrMUWruWSsA/05ChKEkuDNxCq38Yihg0eunvrk7d4sGYbcfM17MKeAl gsC+yt8H5oytqMCNQyI6ODJ3BDyKLztCsmlgMzCz1bekx4ocbRYbq9NBJ3I6CdsT+jPQ /jY5zzEr2TM4BZAzDuK/pczb9KsQmpIy0P7OekIvth7bU4UKVlTajYmXTDEIn8IqPtEN s9k/+Y5OKyFT09nItPhtBXJOJjZ+I22TpG/gXI5exSp9MY3wdZtUzXhkHvKhUJXrVd1w 2O4jC+N0V0t0c9HKDoNTOpkbRAItZKOHPMeubuwh5mkdGPbyutxx+XV4X5szhhXKsMyA ejIg== Received: by 10.43.7.132 with SMTP id oo4mr18758077icb.6.1349881667168; Wed, 10 Oct 2012 08:07:47 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.50.67.148 with SMTP id n20csp238070igt; Wed, 10 Oct 2012 08:07:46 -0700 (PDT) Received: by 10.14.213.65 with SMTP id z41mr3919439eeo.29.1349881665862; Wed, 10 Oct 2012 08:07:45 -0700 (PDT) Received: from mnementh.archaic.org.uk (38.0.169.217.in-addr.arpa. [217.169.0.38]) by mx.google.com with ESMTPS id q5si1146174eep.45.2012.10.10.08.07.45 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 10 Oct 2012 08:07:45 -0700 (PDT) Received-SPF: neutral (google.com: 217.169.0.38 is neither permitted nor denied by best guess record for domain of pm215@archaic.org.uk) client-ip=217.169.0.38; Authentication-Results: mx.google.com; spf=neutral (google.com: 217.169.0.38 is neither permitted nor denied by best guess record for domain of pm215@archaic.org.uk) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1TLxsp-0002C8-SJ; Wed, 10 Oct 2012 16:07:39 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu, patches@linaro.org Subject: [RFC v2 5/6] ARM KVM: save and load VFP registers from kernel Date: Wed, 10 Oct 2012 16:07:38 +0100 Message-Id: <1349881659-8403-6-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1349881659-8403-1-git-send-email-peter.maydell@linaro.org> References: <1349881659-8403-1-git-send-email-peter.maydell@linaro.org> X-Gm-Message-State: ALoCoQl9YFd5CyuRvpJRuW4GHdnPOhmSgNO1ldAgSCSBCRZAfaKUIsbTQqP5Ik9uCQoLdTxA75Q1 Add support for saving and restoring VFP register state from the kernel. This includes a check that the KVM-created CPU has full VFP support (as the TCG Cortex-A15 model always does), since for the moment ARM QEMU doesn't have any way to tweak optional features on created CPUs. Signed-off-by: Peter Maydell --- target-arm/kvm.c | 78 +++++++++++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 75 insertions(+), 3 deletions(-) diff --git a/target-arm/kvm.c b/target-arm/kvm.c index fee60e1..f17e7fd 100644 --- a/target-arm/kvm.c +++ b/target-arm/kvm.c @@ -39,10 +39,28 @@ int kvm_arch_init(KVMState *s) int kvm_arch_init_vcpu(CPUARMState *env) { struct kvm_vcpu_init init; + int ret; + uint64_t v; + struct kvm_one_reg r; init.target = KVM_ARM_TARGET_CORTEX_A15; memset(init.features, 0, sizeof(init.features)); - return kvm_vcpu_ioctl(env, KVM_ARM_VCPU_INIT, &init); + ret = kvm_vcpu_ioctl(env, KVM_ARM_VCPU_INIT, &init); + if (ret) { + return ret; + } + /* Query the kernel to make sure it supports 32 VFP + * registers: QEMU's "cortex-a15" CPU is always a + * VFP-D32 core. The simplest way to do this is just + * to attempt to read register d31. + */ + r.id = KVM_REG_ARM | KVM_REG_SIZE_U64 | KVM_REG_ARM_VFP | 31; + r.addr = (uintptr_t)(&v); + ret = kvm_vcpu_ioctl(env, KVM_GET_ONE_REG, &r); + if (ret == ENOENT) { + return EINVAL; + } + return ret; } struct reg { @@ -68,6 +86,13 @@ struct reg { offsetof(CPUARMState, QEMUFIELD) \ } +#define VFPSYSREG(R) \ + { \ + KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_VFP | \ + KVM_REG_ARM_VFP_##R, \ + offsetof(CPUARMState, vfp.xregs[ARM_VFP_##R]) \ + } + const struct reg regs[] = { /* R0_usr .. R14_usr */ COREREG(usr_regs[0], regs[0]), @@ -115,6 +140,13 @@ const struct reg regs[] = { CP15REG(1, 0, 0, 0, cp15.c1_sys), /* SCTLR */ CP15REG(2, 0, 0, 2, cp15.c2_control), /* TTBCR */ CP15REG(3, 0, 0, 0, cp15.c3), /* DACR */ + /* VFP system registers */ + VFPSYSREG(FPSID), + VFPSYSREG(MVFR1), + VFPSYSREG(MVFR0), + VFPSYSREG(FPEXC), + VFPSYSREG(FPINST), + VFPSYSREG(FPINST2), }; int kvm_arch_put_registers(CPUARMState *env, int level) @@ -122,7 +154,7 @@ int kvm_arch_put_registers(CPUARMState *env, int level) struct kvm_one_reg r; int mode, bn; int ret, i; - uint32_t cpsr; + uint32_t cpsr, fpscr; uint64_t ttbr; /* Make sure the banked regs are properly set */ @@ -173,6 +205,26 @@ int kvm_arch_put_registers(CPUARMState *env, int level) (2 << KVM_REG_ARM_CRM_SHIFT) | (1 << KVM_REG_ARM_OPC1_SHIFT); r.addr = (uintptr_t)(&ttbr); ret = kvm_vcpu_ioctl(env, KVM_SET_ONE_REG, &r); + if (ret) { + return ret; + } + + /* VFP registers */ + r.id = KVM_REG_ARM | KVM_REG_SIZE_U64 | KVM_REG_ARM_VFP; + for (i = 0; i < 32; i++) { + r.addr = (uintptr_t)(&env->vfp.regs[i]); + ret = kvm_vcpu_ioctl(env, KVM_SET_ONE_REG, &r); + if (ret) { + return ret; + } + r.id++; + } + + r.id = KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_VFP | + KVM_REG_ARM_VFP_FPSCR; + fpscr = vfp_get_fpscr(env); + r.addr = (uintptr_t)&fpscr; + ret = kvm_vcpu_ioctl(env, KVM_SET_ONE_REG, &r); return ret; } @@ -182,7 +234,7 @@ int kvm_arch_get_registers(CPUARMState *env) struct kvm_one_reg r; int mode, bn; int ret, i; - uint32_t cpsr; + uint32_t cpsr, fpscr; uint64_t ttbr; for (i = 0; i < ARRAY_SIZE(regs); i++) { @@ -247,6 +299,26 @@ int kvm_arch_get_registers(CPUARMState *env) env->cp15.c2_mask = ~(((uint32_t)0xffffffffu) >> env->cp15.c2_control); env->cp15.c2_base_mask = ~((uint32_t)0x3fffu >> env->cp15.c2_control); + /* VFP registers */ + r.id = KVM_REG_ARM | KVM_REG_SIZE_U64 | KVM_REG_ARM_VFP; + for (i = 0; i < 32; i++) { + r.addr = (uintptr_t)(&env->vfp.regs[i]); + ret = kvm_vcpu_ioctl(env, KVM_GET_ONE_REG, &r); + if (ret) { + return ret; + } + r.id++; + } + + r.id = KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_VFP | + KVM_REG_ARM_VFP_FPSCR; + r.addr = (uintptr_t)&fpscr; + ret = kvm_vcpu_ioctl(env, KVM_GET_ONE_REG, &r); + if (ret) { + return ret; + } + vfp_set_fpscr(env, fpscr); + return 0; }