From patchwork Wed Sep 26 18:48:55 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 11744 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 9F1C124146 for ; Wed, 26 Sep 2012 18:49:10 +0000 (UTC) Received: from mail-ie0-f180.google.com (mail-ie0-f180.google.com [209.85.223.180]) by fiordland.canonical.com (Postfix) with ESMTP id 50CCAA18C60 for ; Wed, 26 Sep 2012 18:49:10 +0000 (UTC) Received: by ieje10 with SMTP id e10so2221680iej.11 for ; Wed, 26 Sep 2012 11:49:09 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=43DMCzvFQRmeauqfPLKay+xyPloJPpbOC8rBOOniPgo=; b=T4xyFvGY3JlUQRXtcv4eBNGKC/zz6+SONq9eHGIHFmFI2d6iG0AS6uGOloNrMOjjxq EF65hDHE1gg5weFOv2Vg5cabZTY8BOCLpFo7Js1eWM0dFXsFcjgHaRbxX8OFgM/0jPJe UPOy4b60y9TbzoMJK1dnnZ8wu3qqbytcX2GjZqb4IEjekJg3UindKptmBcx+XU7uX7at OFMPe+bAksePuNWeqsAYWW7nAUy2+iwjKuWDosr85Kn7kuUAHGZV5MxMw6YwXJ0T1tp/ pfPPGt1BUdDsMJZvUOGLe3m3ahlvFjGlEN4zn1Bq1rnri/VBETIUDpFC2MJLPn1q5ULY cL8A== Received: by 10.50.0.193 with SMTP id 1mr1442147igg.0.1348685349663; Wed, 26 Sep 2012 11:49:09 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.50.184.232 with SMTP id ex8csp373843igc; Wed, 26 Sep 2012 11:49:07 -0700 (PDT) Received: by 10.204.9.130 with SMTP id l2mr1103981bkl.56.1348685346288; Wed, 26 Sep 2012 11:49:06 -0700 (PDT) Received: from mnementh.archaic.org.uk (1.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.d.1.0.0.b.8.0.1.0.0.2.ip6.arpa. [2001:8b0:1d0::1]) by mx.google.com with ESMTPS id hi20si6247318bkc.26.2012.09.26.11.49.03 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 26 Sep 2012 11:49:06 -0700 (PDT) Received-SPF: neutral (google.com: 2001:8b0:1d0::1 is neither permitted nor denied by best guess record for domain of pm215@archaic.org.uk) client-ip=2001:8b0:1d0::1; Authentication-Results: mx.google.com; spf=neutral (google.com: 2001:8b0:1d0::1 is neither permitted nor denied by best guess record for domain of pm215@archaic.org.uk) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1TGwfH-0004Mz-N4; Wed, 26 Sep 2012 19:48:55 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: Richard Henderson , Andrzej Zaborowski , Aurelien Jarno , patches@linaro.org Subject: [PATCH 2/2] tcg/arm: Implement movcond_i32 Date: Wed, 26 Sep 2012 19:48:55 +0100 Message-Id: <1348685335-16770-3-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1348685335-16770-1-git-send-email-peter.maydell@linaro.org> References: <1348685335-16770-1-git-send-email-peter.maydell@linaro.org> X-Gm-Message-State: ALoCoQliv7GvSemqSJsQyduzqdYpPIKQKFFuwbxmLC+xlD72vG+G/lfCKFIT6mQXygqhDoydyQYk Implement movcond_i32 for ARM, as the sequence mov dst, v2 (implicitly done by the tcg common code) cmp c1, c2 movCC dst, v1 Signed-off-by: Peter Maydell Reviewed-by: Aurelien Jarno --- tcg/arm/tcg-target.c | 10 ++++++++++ tcg/arm/tcg-target.h | 2 +- 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c index a83b295..e38fd65 100644 --- a/tcg/arm/tcg-target.c +++ b/tcg/arm/tcg-target.c @@ -1587,6 +1587,15 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_movi_i32: tcg_out_movi32(s, COND_AL, args[0], args[1]); break; + case INDEX_op_movcond_i32: + /* Constraints mean that v2 is always in the same register as dest, + * so we only need to do "if condition passed, move v1 to dest". + */ + tcg_out_dat_rI(s, COND_AL, ARITH_CMP, 0, + args[1], args[2], const_args[2]); + tcg_out_dat_rI(s, tcg_cond_to_arm_cond[args[5]], + ARITH_MOV, args[0], 0, args[3], const_args[3]); + break; case INDEX_op_add_i32: c = ARITH_ADD; goto gen_arith; @@ -1798,6 +1807,7 @@ static const TCGTargetOpDef arm_op_defs[] = { { INDEX_op_brcond_i32, { "r", "rI" } }, { INDEX_op_setcond_i32, { "r", "r", "rI" } }, + { INDEX_op_movcond_i32, { "r", "r", "rI", "rI", "0" } }, /* TODO: "r", "r", "r", "r", "ri", "ri" */ { INDEX_op_add2_i32, { "r", "r", "r", "r", "r", "r" } }, diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index e2299ca..0df3352 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -73,7 +73,7 @@ typedef enum { #define TCG_TARGET_HAS_nand_i32 0 #define TCG_TARGET_HAS_nor_i32 0 #define TCG_TARGET_HAS_deposit_i32 0 -#define TCG_TARGET_HAS_movcond_i32 0 +#define TCG_TARGET_HAS_movcond_i32 1 #define TCG_TARGET_HAS_GUEST_BASE