From patchwork Tue Aug 7 13:51:16 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 10569 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 31C1323F61 for ; Tue, 7 Aug 2012 13:51:31 +0000 (UTC) Received: from mail-yw0-f52.google.com (mail-yw0-f52.google.com [209.85.213.52]) by fiordland.canonical.com (Postfix) with ESMTP id D82E6A18787 for ; Tue, 7 Aug 2012 13:51:30 +0000 (UTC) Received: by yhpp61 with SMTP id p61so1806412yhp.11 for ; Tue, 07 Aug 2012 06:51:30 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=4ZzUdMp0uguIv1t3lmNgnjVxUOvSZwxasmFmSPvPuiM=; b=gThbV3WxprQfJOXeE2ljzHFKd1LiqR3hTUuLw2ORK7Muwf/KVks4JSh29yMxibcDyu NNnxHiFLchQNYeg2rdbIimAOGOPbNDKOJdW8bnXvq06oav1LOcWB73QCaCjZedeE8z+o ZKtbjMAbEo75zvs8kiSotSqsZ5eZNc8fjJkTaWOYAts5e53z0jQ9VFtjUqojQ4wrWnGH YUejNI2QEbHAE0Pd/7vscIJZUdW4qgw+lu3jcVh0cJoqNH4pCIFqpoW9Kn9MR8lgXlJU GDktI+T1N7jBDplDOvpa5wrBCFxx0XD1OTstMJRMxF4pb6FQOF9Oqi7fIrvypEYfwhQh Pfdg== Received: by 10.50.213.39 with SMTP id np7mr8680737igc.51.1344347490105; Tue, 07 Aug 2012 06:51:30 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.50.87.40 with SMTP id u8csp500328igz; Tue, 7 Aug 2012 06:51:26 -0700 (PDT) Received: by 10.180.75.209 with SMTP id e17mr32064458wiw.0.1344347484841; Tue, 07 Aug 2012 06:51:24 -0700 (PDT) Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk. [81.2.115.146]) by mx.google.com with ESMTPS id f20si23117677wiw.5.2012.08.07.06.51.18 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 07 Aug 2012 06:51:24 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) client-ip=81.2.115.146; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1SykBo-00056s-TU; Tue, 07 Aug 2012 14:51:16 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH 2/2] target-arm: Reinstate display of VFP registers in cpu_dump_state Date: Tue, 7 Aug 2012 14:51:16 +0100 Message-Id: <1344347476-19613-3-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1344347476-19613-1-git-send-email-peter.maydell@linaro.org> References: <1344347476-19613-1-git-send-email-peter.maydell@linaro.org> X-Gm-Message-State: ALoCoQlQ9OAufF9AXjZJLM/U9XnVou34q2EyI6qr2nJvkZFITrDM1tBQVdcGmjR5LtXmJGlTYAL0 Reinstate the display of VFP registers in cpu_dump_state(), if the CPU has them (this code had been #if 0'd out a for a long time). We drop the attempt ot display the values as floating point, since this makes assumptions about the host 'float' and 'double' formats and is not done by eg the i386 cpu_dump_state(). This display is gated on the CPU_DUMP_FPU flag, as for x86. Signed-off-by: Peter Maydell --- target-arm/translate.c | 42 ++++++++++++++++-------------------------- 1 file changed, 16 insertions(+), 26 deletions(-) diff --git a/target-arm/translate.c b/target-arm/translate.c index 29008a4..1ada5fc 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -9970,19 +9970,6 @@ void cpu_dump_state(CPUARMState *env, FILE *f, fprintf_function cpu_fprintf, int flags) { int i; -#if 0 - union { - uint32_t i; - float s; - } s0, s1; - CPU_DoubleU d; - /* ??? This assumes float64 and double have the same layout. - Oh well, it's only debug dumps. */ - union { - float64 f64; - double d; - } d0; -#endif uint32_t psr; for(i=0;i<16;i++) { @@ -10002,20 +9989,23 @@ void cpu_dump_state(CPUARMState *env, FILE *f, fprintf_function cpu_fprintf, psr & CPSR_T ? 'T' : 'A', cpu_mode_names[psr & 0xf], (psr & 0x10) ? 32 : 26); -#if 0 - for (i = 0; i < 16; i++) { - d.d = env->vfp.regs[i]; - s0.i = d.l.lower; - s1.i = d.l.upper; - d0.f64 = d.d; - cpu_fprintf(f, "s%02d=%08x(%8g) s%02d=%08x(%8g) d%02d=%08x%08x(%8g)\n", - i * 2, (int)s0.i, s0.s, - i * 2 + 1, (int)s1.i, s1.s, - i, (int)(uint32_t)d.l.upper, (int)(uint32_t)d.l.lower, - d0.d); + if (flags & CPU_DUMP_FPU) { + int numvfpregs = 0; + if (arm_feature(env, ARM_FEATURE_VFP)) { + numvfpregs += 16; + } + if (arm_feature(env, ARM_FEATURE_VFP3)) { + numvfpregs += 16; + } + for (i = 0; i < numvfpregs; i++) { + uint64_t v = float64_val(env->vfp.regs[i]); + cpu_fprintf(f, "s%02d=%08x s%02d=%08x d%02d=%016" PRIx64 "\n", + i * 2, (uint32_t)v, + i * 2 + 1, (uint32_t)(v >> 32), + i, v); + } + cpu_fprintf(f, "FPSCR: %08x\n", (int)env->vfp.xregs[ARM_VFP_FPSCR]); } - cpu_fprintf(f, "FPSCR: %08x\n", (int)env->vfp.xregs[ARM_VFP_FPSCR]); -#endif } void restore_state_to_opc(CPUARMState *env, TranslationBlock *tb, int pc_pos)