From patchwork Thu Jul 5 21:28:59 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 9867 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id BB68D23E4F for ; Thu, 5 Jul 2012 21:29:06 +0000 (UTC) Received: from mail-yx0-f180.google.com (mail-yx0-f180.google.com [209.85.213.180]) by fiordland.canonical.com (Postfix) with ESMTP id 8B814A180D3 for ; Thu, 5 Jul 2012 21:29:06 +0000 (UTC) Received: by yenq6 with SMTP id q6so8570251yen.11 for ; Thu, 05 Jul 2012 14:29:06 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=xJhXdlEbNJNXB/4FD/1C3tdLDIULhrfXyE6WejD4x0I=; b=pXNPPUXNxHTdzgjHS/hftYteLsCxMmDaWAn3LcFe1zXggdFWdvD2zE6QpMKhxhX5nZ 6tSYUL1S2cHJa6ny7S0TdBo+2vUhPDsIDCbxQJcQJ+4BaVGMLBbp+LJIiVHUs4YB/Q6i uhkNQNEI77V2yBEpZxwzby+rqk5ABwhgRl2obqM1zDKvVxiL1+im86N0bv4jOLNBcwDC gY0OFFTU1OnwrcdM4dim3Wy2J6XvCGhjzfEp2Japn3pycqXP0rzyxl1FaT3BL7xTJtbL AbWYD2RJ8mPGEK2MKkMrCgZPWCGcBxinf89YSIxbu/dQFiRY9KkJpOLMTtkfXJN6zTsn euvA== Received: by 10.50.87.227 with SMTP id bb3mr854905igb.57.1341523745841; Thu, 05 Jul 2012 14:29:05 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.24.148 with SMTP id v20csp1076ibb; Thu, 5 Jul 2012 14:29:04 -0700 (PDT) Received: by 10.216.50.73 with SMTP id y51mr1394748web.55.1341523743564; Thu, 05 Jul 2012 14:29:03 -0700 (PDT) Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk. [81.2.115.146]) by mx.google.com with ESMTPS id bm8si2769827wib.11.2012.07.05.14.29.02 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 05 Jul 2012 14:29:03 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) client-ip=81.2.115.146; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1Smtbh-0005uo-02; Thu, 05 Jul 2012 22:29:01 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Stefan Weil , Blue Swirl Subject: [PATCH 2/3] target-i386: Remove confusing X86_64_DEF macro Date: Thu, 5 Jul 2012 22:28:59 +0100 Message-Id: <1341523740-22711-3-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1341523740-22711-1-git-send-email-peter.maydell@linaro.org> References: <1341523740-22711-1-git-send-email-peter.maydell@linaro.org> X-Gm-Message-State: ALoCoQlzW9G72YFYH16RDUhEAAykswrvvsxvAPvW/oN4dXAOkxbl96CPFg7WCTbq4WV+MH0Bg6I3 The X86_64_DEF macro is a confusing way of making some terms in a conditional only appear if TARGET_X86_64 is defined. We only use it in two places, and in both cases this is for making the same test, so abstract that check out into a function where we can use a more conventional #ifdef. Signed-off-by: Peter Maydell --- target-i386/translate.c | 39 ++++++++++++++++++++++++--------------- 1 files changed, 24 insertions(+), 15 deletions(-) diff --git a/target-i386/translate.c b/target-i386/translate.c index 8d696ea..5899e09 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -38,12 +38,10 @@ #define PREFIX_ADR 0x10 #ifdef TARGET_X86_64 -#define X86_64_DEF(...) __VA_ARGS__ #define CODE64(s) ((s)->code64) #define REX_X(s) ((s)->rex_x) #define REX_B(s) ((s)->rex_b) #else -#define X86_64_DEF(...) #define CODE64(s) 0 #define REX_X(s) 0 #define REX_B(s) 0 @@ -265,11 +263,30 @@ static inline void gen_op_andl_A0_ffff(void) #define REG_LH_OFFSET 4 #endif +/* In instruction encodings for byte register accesses the + * register number usually indicates "low 8 bits of register N"; + * however there are some special cases where N 4..7 indicates + * [AH, CH, DH, BH], ie "bits 15..8 of register N-4". Return + * true for this special case, false otherwise. + */ +static inline bool byte_reg_is_xH(int reg) +{ + if (reg < 4) { + return false; + } +#ifdef TARGET_X86_64 + if (reg >= 8 || x86_64_hregs) { + return false; + } +#endif + return true; +} + static inline void gen_op_mov_reg_v(int ot, int reg, TCGv t0) { switch(ot) { case OT_BYTE: - if (reg < 4 X86_64_DEF( || reg >= 8 || x86_64_hregs)) { + if (!byte_reg_is_xH(reg)) { tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], t0, 0, 8); } else { tcg_gen_deposit_tl(cpu_regs[reg - 4], cpu_regs[reg - 4], t0, 8, 8); @@ -324,19 +341,11 @@ static inline void gen_op_mov_reg_A0(int size, int reg) static inline void gen_op_mov_v_reg(int ot, TCGv t0, int reg) { - switch(ot) { - case OT_BYTE: - if (reg < 4 X86_64_DEF( || reg >= 8 || x86_64_hregs)) { - goto std_case; - } else { - tcg_gen_shri_tl(t0, cpu_regs[reg - 4], 8); - tcg_gen_ext8u_tl(t0, t0); - } - break; - default: - std_case: + if (ot == OT_BYTE && byte_reg_is_xH(reg)) { + tcg_gen_shri_tl(t0, cpu_regs[reg - 4], 8); + tcg_gen_ext8u_tl(t0, t0); + } else { tcg_gen_mov_tl(t0, cpu_regs[reg]); - break; } }