From patchwork Thu Jul 5 17:00:51 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 9861 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 7B21023F43 for ; Thu, 5 Jul 2012 17:00:58 +0000 (UTC) Received: from mail-yx0-f180.google.com (mail-yx0-f180.google.com [209.85.213.180]) by fiordland.canonical.com (Postfix) with ESMTP id 4BDD4A18345 for ; Thu, 5 Jul 2012 17:00:58 +0000 (UTC) Received: by yenq6 with SMTP id q6so8248125yen.11 for ; Thu, 05 Jul 2012 10:00:57 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=1bh7XBM01SVshAU0COTPyrkK6aUjzCv7R/WbpAaRDrE=; b=eyG0nJkEHsqXJHukZ4JgWwN2mErtGfoNe2haZ0aXu8PdIKV/Pb8v7j5+TGuAkOhpFm 0+9t//PlmQ9hU4YumpydrWESAkCP240hMtzHjH34h1sXcGO8D33gQ5hugEjTY/SVlgIv 7th8q/+UvUEeHaF/QYDXhNmzbkYdf5pUgRIJ/iQBqLKvaUuZyL9FDCbx+vCFEhuy45Bx L05sEIp/mjKD30mfRqiRYQI6mP0mfLwbbBpn2hRrsDoniKtWRMMR3hPRiRF7vxGQdmhK kq4KNkHC2Yu3nhU5ssySG59RapngEUjEfHnqiuE8JTGq8CoXVLODPJMgSegZaViWMNHm +Ayg== Received: by 10.50.163.99 with SMTP id yh3mr310604igb.53.1341507657670; Thu, 05 Jul 2012 10:00:57 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.24.148 with SMTP id v20csp68397ibb; Thu, 5 Jul 2012 10:00:55 -0700 (PDT) Received: by 10.205.134.6 with SMTP id ia6mr14511122bkc.51.1341507654425; Thu, 05 Jul 2012 10:00:54 -0700 (PDT) Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk. [81.2.115.146]) by mx.google.com with ESMTPS id ig16si3578544bkc.98.2012.07.05.10.00.53 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 05 Jul 2012 10:00:54 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) client-ip=81.2.115.146; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1SmpQC-0005lw-U9; Thu, 05 Jul 2012 18:00:52 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Peter Crosthwaite Subject: [PATCH 5/6] hw/arm_boot.c: Support DTBs which use 64 bit addresses Date: Thu, 5 Jul 2012 18:00:51 +0100 Message-Id: <1341507652-22155-6-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1341507652-22155-1-git-send-email-peter.maydell@linaro.org> References: <1341507652-22155-1-git-send-email-peter.maydell@linaro.org> X-Gm-Message-State: ALoCoQnja8UslfVYu6enRVsJO2tLpP0mpVUpQDwVkNtxB1K8Q4OAb6eoZYDFPyASXNZZAgLqN/CE Support the case where the device tree blob specifies that #address-cells and #size-cells are greater than 1. (This is needed for device trees which can handle 64 bit physical addresses and thus total RAM sizes over 4GB.) Signed-off-by: Peter Maydell Reviewed-by: Peter A. G. Crosthwaite --- hw/arm_boot.c | 36 +++++++++++++++++++++++++++++++++--- 1 files changed, 33 insertions(+), 3 deletions(-) diff --git a/hw/arm_boot.c b/hw/arm_boot.c index 7366427..8203422 100644 --- a/hw/arm_boot.c +++ b/hw/arm_boot.c @@ -216,11 +216,12 @@ static void set_kernel_args_old(const struct arm_boot_info *info) static int load_dtb(target_phys_addr_t addr, const struct arm_boot_info *binfo) { #ifdef CONFIG_FDT - uint32_t mem_reg_property[] = { cpu_to_be32(binfo->loader_start), - cpu_to_be32(binfo->ram_size) }; + uint32_t *mem_reg_property; + uint32_t mem_reg_propsize; void *fdt = NULL; char *filename; int size, rc; + uint32_t acells, scells, hival; filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, binfo->dtb_filename); if (!filename) { @@ -236,8 +237,37 @@ static int load_dtb(target_phys_addr_t addr, const struct arm_boot_info *binfo) } g_free(filename); + acells = qemu_devtree_getprop_cell(fdt, "/", "#address-cells"); + scells = qemu_devtree_getprop_cell(fdt, "/", "#size-cells"); + printf("fdt: acells %d scells %d\n", acells, scells); + if (acells == 0 || scells == 0) { + fprintf(stderr, "dtb file invalid (#address-cells or #size-cells 0)\n"); + return -1; + } + + mem_reg_propsize = acells + scells; + mem_reg_property = g_new0(uint32_t, mem_reg_propsize); + mem_reg_property[acells - 1] = cpu_to_be32(binfo->loader_start); + hival = cpu_to_be32(binfo->loader_start >> 32); + if (acells > 1) { + mem_reg_property[acells - 2] = hival; + } else if (hival != 0) { + fprintf(stderr, "qemu: dtb file not compatible with " + "RAM start address > 4GB\n"); + exit(1); + } + mem_reg_property[acells + scells - 1] = cpu_to_be32(binfo->ram_size); + hival = cpu_to_be32(binfo->ram_size >> 32); + if (scells > 1) { + mem_reg_property[acells + scells - 2] = hival; + } else if (hival != 0) { + fprintf(stderr, "qemu: dtb file not compatible with " + "RAM size > 4GB\n"); + exit(1); + } + rc = qemu_devtree_setprop(fdt, "/memory", "reg", mem_reg_property, - sizeof(mem_reg_property)); + mem_reg_propsize * sizeof(uint32_t)); if (rc < 0) { fprintf(stderr, "couldn't set /memory/reg\n"); }