From patchwork Thu Jun 28 14:35:57 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 9683 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 530F723E37 for ; Thu, 28 Jun 2012 14:36:20 +0000 (UTC) Received: from mail-gg0-f180.google.com (mail-gg0-f180.google.com [209.85.161.180]) by fiordland.canonical.com (Postfix) with ESMTP id 2285CA1893D for ; Thu, 28 Jun 2012 14:36:20 +0000 (UTC) Received: by mail-gg0-f180.google.com with SMTP id f1so2059839ggn.11 for ; Thu, 28 Jun 2012 07:36:20 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=E9rgrOdvzo2OTyWgog8YWtOrGQXR+lAwlFpFKUDB6QE=; b=JiCIFZy5nojAEj8Mf2aujA6TKtSSTvDI2zAephRTbmDUagL29IxXyqmsTnKQuvPZm2 ycqaNLAIFl5IusXQQPnIJ8gozNQY23Y8QRDZ8oQTEwMdNO9cIaSOIFcqCqFKgsFg5Azb rpWYrZL7oPSAJj80DcqHz+KlbonFjm7X3eeP7DgD/NzGOW/ygF5vWJBfn2qOrgL4UqoG C9xjLBypPYg0S8CiCBEX3Y1pZ6uSNfXDa1rpwPLIJ6o5EZdKUEBf4j/8KEr82W7VoS0t d7zwYGYum5DgzkMPrShG1OIXzRzsYWB+8NDVh9lzU3mmUGE1sR5Embxchv87WwmaCYAC i6/A== Received: by 10.50.193.196 with SMTP id hq4mr98113igc.57.1340894178720; Thu, 28 Jun 2012 07:36:18 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.24.148 with SMTP id v20csp43451ibb; Thu, 28 Jun 2012 07:36:14 -0700 (PDT) Received: by 10.216.226.40 with SMTP id a40mr1385045weq.127.1340894173648; Thu, 28 Jun 2012 07:36:13 -0700 (PDT) Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk. [81.2.115.146]) by mx.google.com with ESMTPS id fa8si1046609wib.3.2012.06.28.07.36.13 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 28 Jun 2012 07:36:13 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) client-ip=81.2.115.146; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1SkFpG-0008MO-D7; Thu, 28 Jun 2012 15:36:06 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org Subject: [PATCH 04/13] ARM: Make target_phys_addr_t 64 bits and physaddrs 40 bits Date: Thu, 28 Jun 2012 15:35:57 +0100 Message-Id: <1340894166-32105-5-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1340894166-32105-1-git-send-email-peter.maydell@linaro.org> References: <1340894166-32105-1-git-send-email-peter.maydell@linaro.org> X-Gm-Message-State: ALoCoQlJbg3+fFF5tu1YJtya8jQ2owrrwyQV0jVMAko+MlNse+p/9Zwu3mIIX36d4wynN9tD0EA9 Make target_phys_addr_t 64 bits for ARM targets, and set TARGET_PHYS_ADDR_SPACE_BITS to 40. This should have no effect for ARM boards where physical addresses really are 32 bits (except perhaps a slight performance hit on 32 bit hosts for system emulation) but allows us to implement the Large Physical Address Extensions for Cortex-A15, which mean 40 bit physical addresses. Signed-off-by: Peter Maydell --- configure | 2 +- target-arm/cpu.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/configure b/configure index 9f071b7..8b99262 100755 --- a/configure +++ b/configure @@ -3573,7 +3573,7 @@ case "$target_arch2" in bflt="yes" target_nptl="yes" gdb_xml_files="arm-core.xml arm-vfp.xml arm-vfp3.xml arm-neon.xml" - target_phys_bits=32 + target_phys_bits=64 target_llong_alignment=4 target_libs_softmmu="$fdt_libs" ;; diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 33afa18..aadfca0 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -619,7 +619,7 @@ static inline bool cp_access_ok(CPUARMState *env, #define TARGET_PAGE_BITS 10 #endif -#define TARGET_PHYS_ADDR_SPACE_BITS 32 +#define TARGET_PHYS_ADDR_SPACE_BITS 40 #define TARGET_VIRT_ADDR_SPACE_BITS 32 static inline CPUARMState *cpu_init(const char *cpu_model)