From patchwork Mon May 14 19:03:06 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 8613 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 3D89623E61 for ; Mon, 14 May 2012 19:04:20 +0000 (UTC) Received: from mail-yw0-f52.google.com (mail-yw0-f52.google.com [209.85.213.52]) by fiordland.canonical.com (Postfix) with ESMTP id 0DD64A1880D for ; Mon, 14 May 2012 19:04:19 +0000 (UTC) Received: by yhpp61 with SMTP id p61so5802849yhp.11 for ; Mon, 14 May 2012 12:04:19 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=Q+YUJbtkx9D39v+BPKBtti4UTI8qXZwgc3bmOoG50Mo=; b=NiKuCrh8a1qqfM+akctdlYF82XmZmeKfo6wHuuqNSUTZ6BktJcnKIzUsRNcCUvjYed gWK0dfqtLd8TjLCmxFR5GZFPuGh0SxcCcOGhb0uiiAeVN2ph1NXOXh0HVQNfJyRM8je8 GTECqf7Twk/yzq9tNdxerbRCfFQqsm3goIgfDINCVw6kV7Sa70ULjFLAVuyK4KNT1pOD y5ELxjrT1I9b4DJIty/ySk+c3I+YunD/Gbve9ixP5n5y/0TXgLvCl9hQtrgAqVG5LG/R vlv/4ldXejY0V+aldtSasvviYx9YeEMdX5Aez3OM3RqUZkluLZ/EoHyT1XDNfFM1IqSL bOgQ== Received: by 10.50.195.234 with SMTP id ih10mr237694igc.0.1337022259265; Mon, 14 May 2012 12:04:19 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.35.72 with SMTP id o8csp365971ibd; Mon, 14 May 2012 12:04:18 -0700 (PDT) Received: by 10.216.226.72 with SMTP id a50mr3486644weq.5.1337022257756; Mon, 14 May 2012 12:04:17 -0700 (PDT) Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk. [81.2.115.146]) by mx.google.com with ESMTPS id y4si20042069wec.6.2012.05.14.12.04.16 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 14 May 2012 12:04:17 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) client-ip=81.2.115.146; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1SU0YO-0005n2-Lm; Mon, 14 May 2012 20:03:32 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Paul Brook , =?UTF-8?q?Andreas=20F=C3=A4rber?= , Rusty Russell Subject: [PATCH qom-next v2 07/33] target-arm: Add register_cp_regs_for_features() Date: Mon, 14 May 2012 20:03:06 +0100 Message-Id: <1337022212-22219-8-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1337022212-22219-1-git-send-email-peter.maydell@linaro.org> References: <1337022212-22219-1-git-send-email-peter.maydell@linaro.org> X-Gm-Message-State: ALoCoQkVHlX1IaSZUiIUsUEcOPdk94m2ABROpxCGHWcnN+lXPEXzy700R25qcNZ34H0SzrQrJjEG Add new function register_cp_regs_for_features() as a place to register coprocessor registers dependent on feature flags. Signed-off-by: Peter Maydell --- target-arm/cpu-qom.h | 1 + target-arm/cpu.c | 2 ++ target-arm/helper.c | 11 +++++++++++ 3 files changed, 14 insertions(+), 0 deletions(-) diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h index 848ac2f..4ccfc89 100644 --- a/target-arm/cpu-qom.h +++ b/target-arm/cpu-qom.h @@ -107,5 +107,6 @@ static inline ARMCPU *arm_env_get_cpu(CPUARMState *env) #define ENV_GET_CPU(e) CPU(arm_env_get_cpu(e)) void arm_cpu_realize(ARMCPU *cpu); +void register_cp_regs_for_features(ARMCPU *cpu); #endif diff --git a/target-arm/cpu.c b/target-arm/cpu.c index 6456a3d..1aff266 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -216,6 +216,8 @@ void arm_cpu_realize(ARMCPU *cpu) if (arm_feature(env, ARM_FEATURE_VFP3)) { set_feature(env, ARM_FEATURE_VFP); } + + register_cp_regs_for_features(cpu); } /* CPU models */ diff --git a/target-arm/helper.c b/target-arm/helper.c index dbb3c04..c002050 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -61,6 +61,17 @@ static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) return 0; } +void register_cp_regs_for_features(ARMCPU *cpu) +{ + /* Register all the coprocessor registers based on feature bits */ + CPUARMState *env = &cpu->env; + if (arm_feature(env, ARM_FEATURE_M)) { + /* M profile has no coprocessor registers */ + return; + } + +} + ARMCPU *cpu_arm_init(const char *cpu_model) { ARMCPU *cpu;