From patchwork Mon May 14 19:03:04 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 8634 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 18A6B23EAB for ; Mon, 14 May 2012 19:27:14 +0000 (UTC) Received: from mail-gg0-f180.google.com (mail-gg0-f180.google.com [209.85.161.180]) by fiordland.canonical.com (Postfix) with ESMTP id D3FA7A1880D for ; Mon, 14 May 2012 19:27:13 +0000 (UTC) Received: by mail-gg0-f180.google.com with SMTP id f1so3837754ggn.11 for ; Mon, 14 May 2012 12:27:13 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=cF5DrW1u4g38e8ML4g0R6H2tkmu1TNNaY6mge2zAEW8=; b=PU1eOAdIPD8hFiHH581cPMr0CK2hkB9OhbOSR3a5BWPf5/08IvdITDEi3p0u2RDkPX 3fwT0n+OGOlxgSMEEgT9ORkKmQaHxFgXQlQI0TlppoREpaJBTEn3hFtRzlhTdGfdVBv6 72vX8kcfje1f3z6msFMfqYjybwTAUgKfXS/zc/nSKiv1NJQAFinDtxDbEoRiCblzMP2Y 0dWrZ61bO7fUBli+l1gwVVzUQ9mepnabzrijGfkRkOU3+Vc+k9873YQXfOMx5BDug2H5 JJ9hwgYr7BKGkRDzWFphjtG2hbuwKx9EY/P/sixmPtwCSSOnfO+ONjDiNGtZyWr8csDf c4Og== Received: by 10.42.88.135 with SMTP id c7mr4285910icm.57.1337023633536; Mon, 14 May 2012 12:27:13 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.35.72 with SMTP id o8csp367279ibd; Mon, 14 May 2012 12:27:12 -0700 (PDT) Received: by 10.180.87.35 with SMTP id u3mr22737409wiz.11.1337023631537; Mon, 14 May 2012 12:27:11 -0700 (PDT) Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk. [81.2.115.146]) by mx.google.com with ESMTPS id r6si13645864wif.0.2012.05.14.12.27.10 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 14 May 2012 12:27:11 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) client-ip=81.2.115.146; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1SU0YO-0005my-HX; Mon, 14 May 2012 20:03:32 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Paul Brook , =?UTF-8?q?Andreas=20F=C3=A4rber?= , Rusty Russell Subject: [PATCH qom-next v2 05/33] hw/pxa2xx_pic: Convert coprocessor registers to new scheme Date: Mon, 14 May 2012 20:03:04 +0100 Message-Id: <1337022212-22219-6-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1337022212-22219-1-git-send-email-peter.maydell@linaro.org> References: <1337022212-22219-1-git-send-email-peter.maydell@linaro.org> X-Gm-Message-State: ALoCoQl1kKcikL5ZF+rRDmd7CdMcfFiAaVJbR5s5qauq/Br/V9rFFXv+2u+UEspRophnHSDBnO0a Convert the coprocessor access functions for the pxa2xx PIC to the arm_cp_reginfo scheme. Signed-off-by: Peter Maydell --- hw/pxa2xx_pic.c | 53 +++++++++++++++++++++++++++++++---------------------- 1 files changed, 31 insertions(+), 22 deletions(-) diff --git a/hw/pxa2xx_pic.c b/hw/pxa2xx_pic.c index a806b80..6ba932a 100644 --- a/hw/pxa2xx_pic.c +++ b/hw/pxa2xx_pic.c @@ -206,33 +206,42 @@ static const int pxa2xx_cp_reg_map[0x10] = { [0xa] = ICPR2, }; -static uint32_t pxa2xx_pic_cp_read(void *opaque, int op2, int reg, int crm) +static int pxa2xx_pic_cp_read(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t *value) { - target_phys_addr_t offset; - - if (pxa2xx_cp_reg_map[reg] == -1) { - printf("%s: Bad register 0x%x\n", __FUNCTION__, reg); - return 0; - } - - offset = pxa2xx_cp_reg_map[reg]; - return pxa2xx_pic_mem_read(opaque, offset, 4); + int offset = pxa2xx_cp_reg_map[ri->crn]; + *value = pxa2xx_pic_mem_read(ri->opaque, offset, 4); + return 0; } -static void pxa2xx_pic_cp_write(void *opaque, int op2, int reg, int crm, - uint32_t value) +static int pxa2xx_pic_cp_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) { - target_phys_addr_t offset; - - if (pxa2xx_cp_reg_map[reg] == -1) { - printf("%s: Bad register 0x%x\n", __FUNCTION__, reg); - return; - } - - offset = pxa2xx_cp_reg_map[reg]; - pxa2xx_pic_mem_write(opaque, offset, value, 4); + int offset = pxa2xx_cp_reg_map[ri->crn]; + pxa2xx_pic_mem_write(ri->opaque, offset, value, 4); + return 0; } +#define REGINFO_FOR_PIC_CP(NAME, CRN) \ + { .name = NAME, .cp = 6, .crn = CRN, .crm = 0, .opc1 = 0, .opc2 = 0, \ + .access = PL1_RW, \ + .readfn = pxa2xx_pic_cp_read, .writefn = pxa2xx_pic_cp_write } + +static const ARMCPRegInfo pxa_pic_cp_reginfo[] = { + REGINFO_FOR_PIC_CP("ICIP", 0), + REGINFO_FOR_PIC_CP("ICMR", 1), + REGINFO_FOR_PIC_CP("ICLR", 2), + REGINFO_FOR_PIC_CP("ICFP", 3), + REGINFO_FOR_PIC_CP("ICPR", 4), + REGINFO_FOR_PIC_CP("ICHP", 5), + REGINFO_FOR_PIC_CP("ICIP2", 6), + REGINFO_FOR_PIC_CP("ICMR2", 7), + REGINFO_FOR_PIC_CP("ICLR2", 8), + REGINFO_FOR_PIC_CP("ICFP2", 9), + REGINFO_FOR_PIC_CP("ICPR2", 0xa), + REGINFO_SENTINEL +}; + static const MemoryRegionOps pxa2xx_pic_ops = { .read = pxa2xx_pic_mem_read, .write = pxa2xx_pic_mem_write, @@ -270,7 +279,7 @@ DeviceState *pxa2xx_pic_init(target_phys_addr_t base, CPUARMState *env) sysbus_mmio_map(sysbus_from_qdev(dev), 0, base); /* Enable IC coprocessor access. */ - cpu_arm_set_cp_io(env, 6, pxa2xx_pic_cp_read, pxa2xx_pic_cp_write, s); + define_arm_cp_regs_with_opaque(arm_env_get_cpu(env), pxa_pic_cp_reginfo, s); return dev; }