From patchwork Mon May 14 19:03:30 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 8618 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 5DE5223EAB for ; Mon, 14 May 2012 19:26:51 +0000 (UTC) Received: from mail-gg0-f180.google.com (mail-gg0-f180.google.com [209.85.161.180]) by fiordland.canonical.com (Postfix) with ESMTP id 23C26A1858E for ; Mon, 14 May 2012 19:26:51 +0000 (UTC) Received: by mail-gg0-f180.google.com with SMTP id f1so3837754ggn.11 for ; Mon, 14 May 2012 12:26:51 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=S5kkiZIxZPjyxwuU4eXyDOjF6qQVeVdfJIjPA3jBkQ4=; b=WagwlLi8PiWb3c+snFSaYCZCIqjh+ebfYokC1+bxFRVeltDlZ0GrQMEsZCIRN2AHrx mKOGAUUfgFN7Tzkic9VBbbjAk+EmzXCzhln0v+uce4KksO6pa1/1aB2uGzSsKwiBQ0om jLRP/5dWlFVhMEPecC5W5hrzwieXgfJJEv+ZjS1ZMgZdd/m2WL+Iksft5iU6+0NQFrF3 Kqeme+Qns5teo6QfZqrl0j603do4uNVMCDYRCsUTKdu/GSGLmH01euv5qon2PGjjsEn8 EXJsc/6DjtRdUPsbFqWtlTHPIE/PjxE50tWrl1nC+G/GcXuzjcasvCqCUaBkA/JyWm76 5O2g== Received: by 10.50.203.39 with SMTP id kn7mr4911981igc.53.1337023610805; Mon, 14 May 2012 12:26:50 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.35.72 with SMTP id o8csp367214ibd; Mon, 14 May 2012 12:26:48 -0700 (PDT) Received: by 10.180.82.5 with SMTP id e5mr22746424wiy.0.1337023607713; Mon, 14 May 2012 12:26:47 -0700 (PDT) Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk. [81.2.115.146]) by mx.google.com with ESMTPS id fa8si20812586wib.3.2012.05.14.12.26.46 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 14 May 2012 12:26:47 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) client-ip=81.2.115.146; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1SU0YQ-0005p8-Np; Mon, 14 May 2012 20:03:34 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Paul Brook , =?UTF-8?q?Andreas=20F=C3=A4rber?= , Rusty Russell Subject: [PATCH qom-next v2 31/33] target-arm: Move block cache ops to new cp15 framework Date: Mon, 14 May 2012 20:03:30 +0100 Message-Id: <1337022212-22219-32-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1337022212-22219-1-git-send-email-peter.maydell@linaro.org> References: <1337022212-22219-1-git-send-email-peter.maydell@linaro.org> X-Gm-Message-State: ALoCoQmF0OM/ZytwJp2Q4NYAtti3wTBnk1ykpk4sg/ovKhxSo6IouI+0uh0SyAvvQPaiX0PZYWZW Move the v6 optional block cache ops to the new cp15 framework. This includes only providing them on the CPUs which implemented them, rather than the previous blunderbuss approach of making all MCRR instructions on all CPUs act as NOPs. Signed-off-by: Peter Maydell --- target-arm/helper.c | 13 +++++++++++++ target-arm/translate.c | 7 +------ 2 files changed, 14 insertions(+), 6 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index 753ab5c..805ca98 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -815,6 +815,19 @@ static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = { /* We never have a a block transfer operation in progress */ { .name = "BXSR", .cp = 15, .crn = 7, .crm = 12, .opc1 = 0, .opc2 = 4, .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 }, + /* The cache ops themselves: these all NOP for QEMU */ + { .name = "IICR", .cp = 15, .crm = 5, .opc1 = 0, + .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, + { .name = "IDCR", .cp = 15, .crm = 6, .opc1 = 0, + .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, + { .name = "CDCR", .cp = 15, .crm = 12, .opc1 = 0, + .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, + { .name = "PIR", .cp = 15, .crm = 12, .opc1 = 1, + .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, + { .name = "PDR", .cp = 15, .crm = 12, .opc1 = 2, + .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, + { .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0, + .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, REGINFO_SENTINEL }; diff --git a/target-arm/translate.c b/target-arm/translate.c index f4e9435..fcdc9d3 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -2451,12 +2451,7 @@ static int disas_cp15_insn(CPUARMState *env, DisasContext *s, uint32_t insn) return 1; if ((insn & (1 << 25)) == 0) { - if (insn & (1 << 20)) { - /* mrrc */ - return 1; - } - /* mcrr. Used for block cache operations, so implement as no-op. */ - return 0; + return 1; } if ((insn & (1 << 4)) == 0) { /* cdp */