From patchwork Mon May 14 19:03:29 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 8614 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 504E423EAB for ; Mon, 14 May 2012 19:26:46 +0000 (UTC) Received: from mail-yw0-f52.google.com (mail-yw0-f52.google.com [209.85.213.52]) by fiordland.canonical.com (Postfix) with ESMTP id 12693A1858E for ; Mon, 14 May 2012 19:26:45 +0000 (UTC) Received: by yhpp61 with SMTP id p61so5835105yhp.11 for ; Mon, 14 May 2012 12:26:45 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=dmamEwemIk3vPeb5sG3ADmbdksNjaeaQHmW39rYnf1M=; b=ATJY0ZDsLnar/hTTotnoGHVDTvbU2gBiTEo9UBZghwox7KcVb8zds8eQk9e0hSIuh0 UTsmVmOiEZVu6hfb6AH/xKa2BQrYsCXlCkp/3K298rpDcBNRjozmlmLdGO/wF+doLWjW v4Vybo2/E1J5QXflXaYF35EhRsG+04/KGEBq5UItFCPaxhN9NgKE6aJUd250shoWLm9y yiVYZP+9+BAWG20YnCmMD7HVIslNzDAmf7y0IjQUSGmKJHrnLQSuA3V0sJdpFYE5yA/i JyH3GNeNo1vB2RtEKhVO/x+T509cneUmO06cRIlBscXQj15n8f7B8wn7jB8/4r1cgZzZ a9qQ== Received: by 10.50.195.234 with SMTP id ih10mr276636igc.0.1337023605079; Mon, 14 May 2012 12:26:45 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.35.72 with SMTP id o8csp367202ibd; Mon, 14 May 2012 12:26:40 -0700 (PDT) Received: by 10.180.79.72 with SMTP id h8mr23024623wix.1.1337023599960; Mon, 14 May 2012 12:26:39 -0700 (PDT) Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk. [81.2.115.146]) by mx.google.com with ESMTPS id gg1si20600499wib.43.2012.05.14.12.26.39 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 14 May 2012 12:26:39 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) client-ip=81.2.115.146; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1SU0YQ-0005ox-Ji; Mon, 14 May 2012 20:03:34 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Paul Brook , =?UTF-8?q?Andreas=20F=C3=A4rber?= , Rusty Russell Subject: [PATCH qom-next v2 30/33] target-arm: Remove c0_cachetype CPUARMState field Date: Mon, 14 May 2012 20:03:29 +0100 Message-Id: <1337022212-22219-31-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1337022212-22219-1-git-send-email-peter.maydell@linaro.org> References: <1337022212-22219-1-git-send-email-peter.maydell@linaro.org> X-Gm-Message-State: ALoCoQlm+qbihGoQBuMIrKUK+b48sewWuBgcN9iKAK1Tdb4ng0flgA2fRQCZyzR45B0fzSwAA5AC Remove the no-longer-used CPUARMState c0_cachetype field. Although this was a constant register we had it in our migration state. Drop this (with resulting version bump) because for ARM currently we prefer cleaner migration code and have not stabilised migration format yet. Signed-off-by: Peter Maydell --- target-arm/cpu.h | 3 +-- target-arm/machine.c | 2 -- 2 files changed, 1 insertions(+), 4 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 2630fe7..27e398b 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -107,7 +107,6 @@ typedef struct CPUARMState { /* System control coprocessor (cp15) */ struct { uint32_t c0_cpuid; - uint32_t c0_cachetype; uint32_t c0_cssel; /* Cache size selection. */ uint32_t c1_sys; /* System control register. */ uint32_t c1_coproc; /* Coprocessor access register. */ @@ -664,7 +663,7 @@ static inline CPUARMState *cpu_init(const char *cpu_model) #define cpu_signal_handler cpu_arm_signal_handler #define cpu_list arm_cpu_list -#define CPU_SAVE_VERSION 6 +#define CPU_SAVE_VERSION 7 /* MMU modes definitions */ #define MMU_MODE0_SUFFIX _kernel diff --git a/target-arm/machine.c b/target-arm/machine.c index f66b8df..a2a75fb 100644 --- a/target-arm/machine.c +++ b/target-arm/machine.c @@ -21,7 +21,6 @@ void cpu_save(QEMUFile *f, void *opaque) qemu_put_be32(f, env->fiq_regs[i]); } qemu_put_be32(f, env->cp15.c0_cpuid); - qemu_put_be32(f, env->cp15.c0_cachetype); qemu_put_be32(f, env->cp15.c0_cssel); qemu_put_be32(f, env->cp15.c1_sys); qemu_put_be32(f, env->cp15.c1_coproc); @@ -139,7 +138,6 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id) env->fiq_regs[i] = qemu_get_be32(f); } env->cp15.c0_cpuid = qemu_get_be32(f); - env->cp15.c0_cachetype = qemu_get_be32(f); env->cp15.c0_cssel = qemu_get_be32(f); env->cp15.c1_sys = qemu_get_be32(f); env->cp15.c1_coproc = qemu_get_be32(f);