From patchwork Mon May 14 19:03:27 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 8617 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id B67FD23EAB for ; Mon, 14 May 2012 19:26:50 +0000 (UTC) Received: from mail-gg0-f180.google.com (mail-gg0-f180.google.com [209.85.161.180]) by fiordland.canonical.com (Postfix) with ESMTP id 709FCA18822 for ; Mon, 14 May 2012 19:26:50 +0000 (UTC) Received: by ggnf1 with SMTP id f1so3837754ggn.11 for ; Mon, 14 May 2012 12:26:50 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=mJTa7kSD7FoXk7OjReGAIAV+EsVLYRt9n1t4E3iSYfo=; b=PwzJK3goGKJT3zWbpGz2Xmpi5PIL7GTY2mHQsw3IneiEodGfkhba4mflqhMAkrufrf xm5j3HLlkGNWtOGPl2ix+ThV5HOCdfDpHULiv0r6xAMSyVJ+GEpZtZF9P4iBEMFldASj XhtWr7MjnEX6EWEilTP9TaqIG0prbLDeF3vWza+n0+Nc8AtO+A3BEzA6j27qo4GtQsC6 KIDHWnJpeMOaZZNGqj5LED8E6f4lS/iQwEkfvrE73aUPBmHhINX2Z0iW8Z44c/XP0IzJ 51YzwbYIBJnaEgioY6MLTFdroh4DL0RJ69cEX/fw9XATCGMzSb1fWZBg3gGRE5lhrm3l NkQQ== Received: by 10.42.89.72 with SMTP id f8mr2659702icm.33.1337023609823; Mon, 14 May 2012 12:26:49 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.35.72 with SMTP id o8csp367212ibd; Mon, 14 May 2012 12:26:47 -0700 (PDT) Received: by 10.180.105.194 with SMTP id go2mr910574wib.22.1337023606866; Mon, 14 May 2012 12:26:46 -0700 (PDT) Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk. [81.2.115.146]) by mx.google.com with ESMTPS id 45si20090544wej.55.2012.05.14.12.26.45 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 14 May 2012 12:26:46 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) client-ip=81.2.115.146; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1SU0YQ-0005ni-9X; Mon, 14 May 2012 20:03:34 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Paul Brook , =?UTF-8?q?Andreas=20F=C3=A4rber?= , Rusty Russell Subject: [PATCH qom-next v2 28/33] target-arm: Convert MPIDR Date: Mon, 14 May 2012 20:03:27 +0100 Message-Id: <1337022212-22219-29-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1337022212-22219-1-git-send-email-peter.maydell@linaro.org> References: <1337022212-22219-1-git-send-email-peter.maydell@linaro.org> X-Gm-Message-State: ALoCoQlAAKTFKSOjwMb1RhVqgPDQ32IFshdUsE2f3Y3IqszjshTY9+YBygg+NwtokGJlFNQmhk5u Convert the MPIDR to the new cp15 register scheme. This includes giving it its own feature bit rather than doing a CPUID value check. Signed-off-by: Peter Maydell --- target-arm/cpu.c | 2 ++ target-arm/cpu.h | 1 + target-arm/helper.c | 50 ++++++++++++++++++++++++++++---------------------- 3 files changed, 31 insertions(+), 22 deletions(-) diff --git a/target-arm/cpu.c b/target-arm/cpu.c index f4c9116..0c031ba 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -162,6 +162,7 @@ void arm_cpu_realize(ARMCPU *cpu) if (arm_feature(env, ARM_FEATURE_V7)) { set_feature(env, ARM_FEATURE_VAPA); set_feature(env, ARM_FEATURE_THUMB2); + set_feature(env, ARM_FEATURE_MPIDR); if (!arm_feature(env, ARM_FEATURE_M)) { set_feature(env, ARM_FEATURE_V6K); } else { @@ -350,6 +351,7 @@ static void arm11mpcore_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V6K); set_feature(&cpu->env, ARM_FEATURE_VFP); set_feature(&cpu->env, ARM_FEATURE_VAPA); + set_feature(&cpu->env, ARM_FEATURE_MPIDR); set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); cpu->midr = ARM_CPUID_ARM11MPCORE; cpu->reset_fpsid = 0x410120b4; diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 0b984d8..2630fe7 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -386,6 +386,7 @@ enum arm_features { ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */ ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */ ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */ + ARM_FEATURE_MPIDR, /* has cp15 MPIDR */ }; static inline int arm_feature(CPUARMState *env, int feature) diff --git a/target-arm/helper.c b/target-arm/helper.c index eca7d8b..45b3e5b 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -838,6 +838,31 @@ static const ARMCPRegInfo strongarm_cp_reginfo[] = { REGINFO_SENTINEL }; +static int mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t *value) +{ + uint32_t mpidr = env->cpu_index; + /* We don't support setting cluster ID ([8..11]) + * so these bits always RAZ. + */ + if (arm_feature(env, ARM_FEATURE_V7MP)) { + mpidr |= (1 << 31); + /* Cores which are uniprocessor (non-coherent) + * but still implement the MP extensions set + * bit 30. (For instance, A9UP.) However we do + * not currently model any of those cores. + */ + } + *value = mpidr; + return 0; +} + +static const ARMCPRegInfo mpidr_cp_reginfo[] = { + { .name = "MPIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5, + .access = PL1_R, .readfn = mpidr_read }, + REGINFO_SENTINEL +}; + static int sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { env->cp15.c1_sys = value; @@ -980,6 +1005,9 @@ void register_cp_regs_for_features(ARMCPU *cpu) if (arm_feature(env, ARM_FEATURE_DUMMY_C15_REGS)) { define_arm_cp_regs(cpu, dummy_c15_cp_reginfo); } + if (arm_feature(env, ARM_FEATURE_MPIDR)) { + define_arm_cp_regs(cpu, mpidr_cp_reginfo); + } if (arm_feature(env, ARM_FEATURE_AUXCR)) { ARMCPRegInfo auxcr = { .name = "AUXCR", .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1, @@ -2126,28 +2154,6 @@ uint32_t HELPER(get_cp15)(CPUARMState *env, uint32_t insn) return 0; case 3: /* TLB type register. */ return 0; /* No lockable TLB entries. */ - case 5: /* MPIDR */ - /* The MPIDR was standardised in v7; prior to - * this it was implemented only in the 11MPCore. - * For all other pre-v7 cores it does not exist. - */ - if (arm_feature(env, ARM_FEATURE_V7) || - ARM_CPUID(env) == ARM_CPUID_ARM11MPCORE) { - int mpidr = env->cpu_index; - /* We don't support setting cluster ID ([8..11]) - * so these bits always RAZ. - */ - if (arm_feature(env, ARM_FEATURE_V7MP)) { - mpidr |= (1 << 31); - /* Cores which are uniprocessor (non-coherent) - * but still implement the MP extensions set - * bit 30. (For instance, A9UP.) However we do - * not currently model any of those cores. - */ - } - return mpidr; - } - /* otherwise fall through to the unimplemented-reg case */ default: goto bad_reg; }