From patchwork Mon May 14 19:03:22 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 8623 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 7D75823EAB for ; Mon, 14 May 2012 19:26:59 +0000 (UTC) Received: from mail-pz0-f52.google.com (mail-pz0-f52.google.com [209.85.210.52]) by fiordland.canonical.com (Postfix) with ESMTP id 0B98DA18811 for ; Mon, 14 May 2012 19:26:58 +0000 (UTC) Received: by dano14 with SMTP id o14so7666950dan.11 for ; Mon, 14 May 2012 12:26:58 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=oaEGbxf8VPfOSQ9It5CsJ5c1nYKAVW15pVxX+zlRmD8=; b=CLYjUeETpxdlmQ5CCLsI0apSx0iD1JmFW1eYd6ABw1F+vwN83KbBHf0CxrPuO6p4F/ Qb5iFe041yrhnaonvNBY/w2vDA/K5ikr4Q0V1BisLcUgntTC1y1lYGHKTABr/38ZYapy yXzy5/sqlXQ+n7Z6EUxumBTGAJvayFAkI7OqaVjkP4LqBZMSaB1FwFNiBD9jM4ph1ORl Xn9+0HAQmywSpfRn0pKnYvgwHHfVXanwdsrQVM0iwtvW7mAv60lDvkB1CsDgo+g1mUM8 5VyjfXLAVyRNy8gqymouqdQY90JO/HqD50kyKELZjjjCdhyMJCgXVHY1HG/h6afyukK2 iyBw== Received: by 10.50.85.163 with SMTP id i3mr4925343igz.57.1337023618049; Mon, 14 May 2012 12:26:58 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.35.72 with SMTP id o8csp367227ibd; Mon, 14 May 2012 12:26:57 -0700 (PDT) Received: by 10.216.132.75 with SMTP id n53mr5844875wei.51.1337023616160; Mon, 14 May 2012 12:26:56 -0700 (PDT) Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk. [81.2.115.146]) by mx.google.com with ESMTPS id o47si3862905wee.59.2012.05.14.12.26.55 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 14 May 2012 12:26:56 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) client-ip=81.2.115.146; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1SU0YP-0005nY-V4; Mon, 14 May 2012 20:03:33 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Paul Brook , =?UTF-8?q?Andreas=20F=C3=A4rber?= , Rusty Russell Subject: [PATCH qom-next v2 23/33] target-arm: Convert cp15 crn=6 registers Date: Mon, 14 May 2012 20:03:22 +0100 Message-Id: <1337022212-22219-24-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1337022212-22219-1-git-send-email-peter.maydell@linaro.org> References: <1337022212-22219-1-git-send-email-peter.maydell@linaro.org> X-Gm-Message-State: ALoCoQm2P2aPyUviN+IFRRLmv+P4BqDEo0D38V7hlvOQR0q2TQAxpWSYC6ujPPs4mXVYbLPpWjWF Convert the cp15 crn=6 registers to the new scheme. Note that this includes some minor tidyup: drop an unnecessary underdecoding of op2 on OMAPCP cores, and only implement the pre-v6 c6,c0,0,1 IFAR on the 1026 and not on the other ARMv5 cores, which didn't have it. Signed-off-by: Peter Maydell --- target-arm/cpu.c | 10 ++++++ target-arm/helper.c | 88 ++++++++++++++++++++------------------------------ 2 files changed, 45 insertions(+), 53 deletions(-) diff --git a/target-arm/cpu.c b/target-arm/cpu.c index f8534a7..f37380f 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -251,6 +251,16 @@ static void arm1026_initfn(Object *obj) cpu->reset_fpsid = 0x410110a0; cpu->ctr = 0x1dd20d2; cpu->reset_sctlr = 0x00090078; + { + /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */ + ARMCPRegInfo ifar = { + .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1, + .access = PL1_RW, + .fieldoffset = offsetof(CPUARMState, cp15.c6_insn), + .resetvalue = 0 + }; + define_one_arm_cp_reg(cpu, &ifar); + } } static void arm1136_r2_initfn(Object *obj) diff --git a/target-arm/helper.c b/target-arm/helper.c index 300ee62..4a0df3a 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -202,6 +202,14 @@ static const ARMCPRegInfo v6_cp_reginfo[] = { .access = PL0_W, .type = ARM_CP_NOP }, { .name = "ISB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 5, .access = PL0_W, .type = ARM_CP_NOP }, + { .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 2, + .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c6_insn), + .resetvalue = 0, }, + /* Watchpoint Fault Address Register : should actually only be present + * for 1136, 1176, 11MPCore. + */ + { .name = "WFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1, + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, }, REGINFO_SENTINEL }; @@ -545,6 +553,26 @@ static int pmsav5_insn_ap_read(CPUARMState *env, const ARMCPRegInfo *ri, return 0; } +static int arm946_prbs_read(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t *value) +{ + if (ri->crm > 8) { + return EXCP_UDEF; + } + *value = env->cp15.c6_region[ri->crm]; + return 0; +} + +static int arm946_prbs_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + if (ri->crm > 8) { + return EXCP_UDEF; + } + env->cp15.c6_region[ri->crm] = value; + return 0; +} + static const ARMCPRegInfo pmsav5_cp_reginfo[] = { { .name = "DATA_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0, .access = PL1_RW, @@ -566,6 +594,10 @@ static const ARMCPRegInfo pmsav5_cp_reginfo[] = { { .name = "ICACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c2_insn), .resetvalue = 0, }, + /* Protection region base and size registers */ + { .name = "946_PRBS", .cp = 15, .crn = 6, .crm = CP_ANY, .opc1 = 0, + .opc2 = CP_ANY, .access = PL1_RW, + .readfn = arm946_prbs_read, .writefn = arm946_prbs_write, }, REGINFO_SENTINEL }; @@ -603,6 +635,9 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = { .access = PL1_RW, .writefn = vmsa_ttbcr_write, .resetfn = vmsa_ttbcr_reset, .fieldoffset = offsetof(CPUARMState, cp15.c2_control) }, + { .name = "DFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0, + .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c6_data), + .resetvalue = 0, }, REGINFO_SENTINEL }; @@ -1932,27 +1967,6 @@ void HELPER(set_cp15)(CPUARMState *env, uint32_t insn, uint32_t val) break; case 4: /* Reserved. */ goto bad_reg; - case 6: /* MMU Fault address / MPU base/size. */ - if (arm_feature(env, ARM_FEATURE_MPU)) { - if (crm >= 8) - goto bad_reg; - env->cp15.c6_region[crm] = val; - } else { - if (arm_feature(env, ARM_FEATURE_OMAPCP)) - op2 = 0; - switch (op2) { - case 0: - env->cp15.c6_data = val; - break; - case 1: /* ??? This is WFAR on armv6 */ - case 2: - env->cp15.c6_insn = val; - break; - default: - goto bad_reg; - } - } - break; case 9: if (arm_feature(env, ARM_FEATURE_OMAPCP)) break; @@ -2126,38 +2140,6 @@ uint32_t HELPER(get_cp15)(CPUARMState *env, uint32_t insn) } case 4: /* Reserved. */ goto bad_reg; - case 6: /* MMU Fault address. */ - if (arm_feature(env, ARM_FEATURE_MPU)) { - if (crm >= 8) - goto bad_reg; - return env->cp15.c6_region[crm]; - } else { - if (arm_feature(env, ARM_FEATURE_OMAPCP)) - op2 = 0; - switch (op2) { - case 0: - return env->cp15.c6_data; - case 1: - if (arm_feature(env, ARM_FEATURE_V6)) { - /* Watchpoint Fault Adrress. */ - return 0; /* Not implemented. */ - } else { - /* Instruction Fault Adrress. */ - /* Arm9 doesn't have an IFAR, but implementing it anyway - shouldn't do any harm. */ - return env->cp15.c6_insn; - } - case 2: - if (arm_feature(env, ARM_FEATURE_V6)) { - /* Instruction Fault Adrress. */ - return env->cp15.c6_insn; - } else { - goto bad_reg; - } - default: - goto bad_reg; - } - } case 9: switch (crm) { case 0: /* Cache lockdown */