From patchwork Mon May 14 19:03:16 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 8611 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id C6EA323E61 for ; Mon, 14 May 2012 19:03:47 +0000 (UTC) Received: from mail-yw0-f52.google.com (mail-yw0-f52.google.com [209.85.213.52]) by fiordland.canonical.com (Postfix) with ESMTP id 96CF8A18822 for ; Mon, 14 May 2012 19:03:47 +0000 (UTC) Received: by mail-yw0-f52.google.com with SMTP id p61so5801914yhp.11 for ; Mon, 14 May 2012 12:03:47 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=upUiqg5c7eHD+1Sb2twqanqnbzsEiEq++mtW+A7gi7c=; b=BbdoXoZmXZRXcFn5EpLs1pwBQ/Wluudgee7OU/Bgsn5aEHONTcGW+GM27Khol8ygW9 GFruXnhJlKIs6R3oULTvGRiq0fkjFy/70y+5orm3RdsknhYrOYs+wgamO6BAUwmda3jQ XsAeHNucO8aFrHR2rdu7Qn7AWMcD89sGFf9flhZT+P96oLcvWaJ8M7SujsHGySQWmSSk GixW1KxxbJ5RwnP4sdHLzYIgoeQyE9C4uqu738gW1MMvqF5imu7vGznBSCPsRlN3Z0Vm WJSKPNaHo5PoWpXUJ+zMVikl36HzjnD2CqKikly7l8dcTqnu1GocaJWmtlDQ0y9Zu4e2 pATw== Received: by 10.50.87.227 with SMTP id bb3mr137531igb.57.1337022227232; Mon, 14 May 2012 12:03:47 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.35.72 with SMTP id o8csp365943ibd; Mon, 14 May 2012 12:03:42 -0700 (PDT) Received: by 10.216.194.137 with SMTP id m9mr4819358wen.66.1337022220692; Mon, 14 May 2012 12:03:40 -0700 (PDT) Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk. [81.2.115.146]) by mx.google.com with ESMTPS id d7si20519523wid.26.2012.05.14.12.03.39 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 14 May 2012 12:03:40 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) client-ip=81.2.115.146; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1SU0YP-0005nM-HK; Mon, 14 May 2012 20:03:33 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Paul Brook , =?UTF-8?q?Andreas=20F=C3=A4rber?= , Rusty Russell Subject: [PATCH qom-next v2 17/33] target-arm: Convert cp15 crn=13 registers Date: Mon, 14 May 2012 20:03:16 +0100 Message-Id: <1337022212-22219-18-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1337022212-22219-1-git-send-email-peter.maydell@linaro.org> References: <1337022212-22219-1-git-send-email-peter.maydell@linaro.org> X-Gm-Message-State: ALoCoQnC0+grzwusEmKj2Ma+yiI6Yp4197CtPyxWyzQT5OsKWZDzWJAle5Y4WgLM/AGJWvUY/LEu Convert the cp15 crn=13 registers (FCSEIDR, CONTEXTIDR, and the ARM946 Trace Process Identifier Register). Signed-off-by: Peter Maydell --- target-arm/helper.c | 61 ++++++++++++++++++++++++++------------------------- 1 files changed, 31 insertions(+), 30 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index 93300cc..c19ba9e 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -68,6 +68,31 @@ static int dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) return 0; } +static int fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) +{ + if (env->cp15.c13_fcse != value) { + /* Unlike real hardware the qemu TLB uses virtual addresses, + * not modified virtual addresses, so this causes a TLB flush. + */ + tlb_flush(env, 1); + env->cp15.c13_fcse = value; + } + return 0; +} +static int contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + if (env->cp15.c13_context != value && !arm_feature(env, ARM_FEATURE_MPU)) { + /* For VMSA (when not using the LPAE long descriptor page table + * format) this register includes the ASID, so do a TLB flush. + * For PMSA it is purely a process ID and no action is needed. + */ + tlb_flush(env, 1); + } + env->cp15.c13_context = value; + return 0; +} + static const ARMCPRegInfo cp_reginfo[] = { /* DBGDIDR: just RAZ. In particular this means the "debug architecture * version" bits will read as a reserved value, which should cause @@ -80,6 +105,12 @@ static const ARMCPRegInfo cp_reginfo[] = { .crn = 3, .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c3), .resetvalue = 0, .writefn = dacr_write }, + { .name = "FCSEIDR", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 0, + .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c13_fcse), + .resetvalue = 0, .writefn = fcse_write }, + { .name = "CONTEXTIDR", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 1, + .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c13_fcse), + .resetvalue = 0, .writefn = contextidr_write }, REGINFO_SENTINEL }; @@ -1774,27 +1805,6 @@ void HELPER(set_cp15)(CPUARMState *env, uint32_t insn, uint32_t val) break; case 12: /* Reserved. */ goto bad_reg; - case 13: /* Process ID. */ - switch (op2) { - case 0: - /* Unlike real hardware the qemu TLB uses virtual addresses, - not modified virtual addresses, so this causes a TLB flush. - */ - if (env->cp15.c13_fcse != val) - tlb_flush(env, 1); - env->cp15.c13_fcse = val; - break; - case 1: - /* This changes the ASID, so do a TLB flush. */ - if (env->cp15.c13_context != val - && !arm_feature(env, ARM_FEATURE_MPU)) - tlb_flush(env, 0); - env->cp15.c13_context = val; - break; - default: - goto bad_reg; - } - break; case 15: /* Implementation specific. */ if (arm_feature(env, ARM_FEATURE_XSCALE)) { if (op2 == 0 && crm == 1) { @@ -2076,15 +2086,6 @@ uint32_t HELPER(get_cp15)(CPUARMState *env, uint32_t insn) case 11: /* TCM DMA control. */ case 12: /* Reserved. */ goto bad_reg; - case 13: /* Process ID. */ - switch (op2) { - case 0: - return env->cp15.c13_fcse; - case 1: - return env->cp15.c13_context; - default: - goto bad_reg; - } case 15: /* Implementation specific. */ if (arm_feature(env, ARM_FEATURE_XSCALE)) { if (op2 == 0 && crm == 1)