From patchwork Mon May 14 19:03:13 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 8631 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 1549C23EAB for ; Mon, 14 May 2012 19:27:10 +0000 (UTC) Received: from mail-gg0-f180.google.com (mail-gg0-f180.google.com [209.85.161.180]) by fiordland.canonical.com (Postfix) with ESMTP id D8DFCA18822 for ; Mon, 14 May 2012 19:27:09 +0000 (UTC) Received: by mail-gg0-f180.google.com with SMTP id f1so3837754ggn.11 for ; Mon, 14 May 2012 12:27:09 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=gXzGK+XgSdZ0fAlJBK/8x7ZY2QA+jnBHz2Otx2aw7NA=; b=i1Nga9kEvuEerGolME3qEjBAGi95BwVmy6Qq2w8wM3TarQvvizThHGI6vwnHkJf94f uO13tIkKRSv+THLx/3jNfNWHXJWGIA8e0mJT0RHzgggZkmdvma3ZUq36goxY33UaTw2h BzCoipeIL6+QJFp+7UWE2Ta3zk2qQCfJvXaxHnBcITlRLbrMtG5e97BC2ygiLxU4Dn5+ LseHRxAAGnUBSsIqty1QQ0cP49LpCe06px7JZHTScU60FfVMFTVXA2Q9gbe+8mYuL45f DoQyMYDg01mVe+6/uVckpcHhoFxSCakUNWKFTY/mRkoW9PDEmbBilc53mkCy7LApjuIe LKUQ== Received: by 10.50.185.233 with SMTP id ff9mr4957126igc.57.1337023629387; Mon, 14 May 2012 12:27:09 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.35.72 with SMTP id o8csp367252ibd; Mon, 14 May 2012 12:27:06 -0700 (PDT) Received: by 10.180.20.137 with SMTP id n9mr11237035wie.3.1337023625683; Mon, 14 May 2012 12:27:05 -0700 (PDT) Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk. [81.2.115.146]) by mx.google.com with ESMTPS id u3si20613612wia.1.2012.05.14.12.27.04 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 14 May 2012 12:27:05 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) client-ip=81.2.115.146; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1SU0YP-0005nG-AL; Mon, 14 May 2012 20:03:33 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Paul Brook , =?UTF-8?q?Andreas=20F=C3=A4rber?= , Rusty Russell Subject: [PATCH qom-next v2 14/33] target-arm: Convert cp15 c3 register Date: Mon, 14 May 2012 20:03:13 +0100 Message-Id: <1337022212-22219-15-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1337022212-22219-1-git-send-email-peter.maydell@linaro.org> References: <1337022212-22219-1-git-send-email-peter.maydell@linaro.org> X-Gm-Message-State: ALoCoQkrkZU1iRSy2zHzO9eWBg806W7GB4Lk9rKPuDJqxTrsaTt2alZs0jkgB9OpnPlxTguu3WFS Convert the cp15 c3 register (MMU domain access control or MPU write buffer control). NB that this is horribly underdecoded for modern cores (should be crn=3,crm=0, opc1=0,opc2=0) but this change preserves the existing QEMU behaviour. Signed-off-by: Peter Maydell --- target-arm/helper.c | 18 ++++++++++++------ 1 files changed, 12 insertions(+), 6 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index a92bbc7..0f94c2f 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -61,6 +61,13 @@ static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) return 0; } +static int dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) +{ + env->cp15.c3 = value; + tlb_flush(env, 1); /* Flush TLB as domain not tracked in TLB */ + return 0; +} + static const ARMCPRegInfo cp_reginfo[] = { /* DBGDIDR: just RAZ. In particular this means the "debug architecture * version" bits will read as a reserved value, which should cause @@ -68,6 +75,11 @@ static const ARMCPRegInfo cp_reginfo[] = { */ { .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0, .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 }, + /* MMU Domain access control / MPU write buffer control */ + { .name = "DACR", .cp = 15, + .crn = 3, .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, + .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c3), + .resetvalue = 0, .writefn = dacr_write }, REGINFO_SENTINEL }; @@ -1556,10 +1568,6 @@ void HELPER(set_cp15)(CPUARMState *env, uint32_t insn, uint32_t val) } } break; - case 3: /* MMU Domain access control / MPU write buffer control. */ - env->cp15.c3 = val; - tlb_flush(env, 1); /* Flush TLB as domain not tracked in TLB */ - break; case 4: /* Reserved. */ goto bad_reg; case 5: /* MMU Fault status / MPU access permission. */ @@ -1947,8 +1955,6 @@ uint32_t HELPER(get_cp15)(CPUARMState *env, uint32_t insn) goto bad_reg; } } - case 3: /* MMU Domain access control / MPU write buffer control. */ - return env->cp15.c3; case 4: /* Reserved. */ goto bad_reg; case 5: /* MMU Fault status / MPU access permission. */