From patchwork Mon May 14 19:03:12 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 8629 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id D435523EAB for ; Mon, 14 May 2012 19:27:07 +0000 (UTC) Received: from mail-pz0-f52.google.com (mail-pz0-f52.google.com [209.85.210.52]) by fiordland.canonical.com (Postfix) with ESMTP id 68445A1880D for ; Mon, 14 May 2012 19:27:07 +0000 (UTC) Received: by mail-pz0-f52.google.com with SMTP id o14so7666950dan.11 for ; Mon, 14 May 2012 12:27:07 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=ggoHvsdTH9iSxTcdNtluPH4ZMziSoH6fZD0GujsTD3o=; b=pGuVyF/akt4svvQfVxprI3MRBgamX27WlTVyVvkzI29ff1Rv/DGA3hDJ22JgzchGfG YmY9l0GrOm/XM9hAfspWFIMGlMQGZOc9knEpH5OvwfsyTIbYuYi8GtY6wIYsSeeO8b2d //XJdwJxU8qexV0/SWANRod95u/P1nzNKs592Mc+yJZG6b+chqAArD6CCulYMXnvUEzD y3F1DkuPeKXeSCHkEt5nqjYhFJKFGkuw2OxaZa1hdUcbLTm5xHaq0LMpoLiP0H+c7kO/ RbvRKNd7v4ytpDotqjpjDtZSRkWLdbe/1YyFRYspm8tfFICz//lh4hvEFcNLpsm3T61X KAfQ== Received: by 10.50.154.169 with SMTP id vp9mr4947482igb.53.1337023626887; Mon, 14 May 2012 12:27:06 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.35.72 with SMTP id o8csp367248ibd; Mon, 14 May 2012 12:27:05 -0700 (PDT) Received: by 10.180.101.136 with SMTP id fg8mr22904553wib.4.1337023624494; Mon, 14 May 2012 12:27:04 -0700 (PDT) Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk. [81.2.115.146]) by mx.google.com with ESMTPS id z55si16803727wem.97.2012.05.14.12.27.03 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 14 May 2012 12:27:04 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) client-ip=81.2.115.146; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1SU0YP-0005nE-8E; Mon, 14 May 2012 20:03:33 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Paul Brook , =?UTF-8?q?Andreas=20F=C3=A4rber?= , Rusty Russell Subject: [PATCH qom-next v2 13/33] target-arm: Convert generic timer cp15 regs Date: Mon, 14 May 2012 20:03:12 +0100 Message-Id: <1337022212-22219-14-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1337022212-22219-1-git-send-email-peter.maydell@linaro.org> References: <1337022212-22219-1-git-send-email-peter.maydell@linaro.org> X-Gm-Message-State: ALoCoQkZ3eksqzeZrWmmz1weIuLck0x/aS8MRDY3SttRFCcwDMAvNbSnrhpFB12jTKporLgESvWG Convert the (dummy) generic timer cp15 implementation. Signed-off-by: Peter Maydell --- target-arm/helper.c | 23 +++++++++++------------ 1 files changed, 11 insertions(+), 12 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index 88f7ca7..a92bbc7 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -322,6 +322,14 @@ static const ARMCPRegInfo v6k_cp_reginfo[] = { REGINFO_SENTINEL }; +static const ARMCPRegInfo generic_timer_cp_reginfo[] = { + /* Dummy implementation: RAZ/WI the whole crn=14 space */ + { .name = "GENERIC_TIMER", .cp = 15, .crn = 14, + .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, + REGINFO_SENTINEL +}; + void register_cp_regs_for_features(ARMCPU *cpu) { /* Register all the coprocessor registers based on feature bits */ @@ -358,6 +366,9 @@ void register_cp_regs_for_features(ARMCPU *cpu) if (arm_feature(env, ARM_FEATURE_THUMB2EE)) { define_arm_cp_regs(cpu, t2ee_cp_reginfo); } + if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) { + define_arm_cp_regs(cpu, generic_timer_cp_reginfo); + } } ARMCPU *cpu_arm_init(const char *cpu_model) @@ -1725,12 +1736,6 @@ void HELPER(set_cp15)(CPUARMState *env, uint32_t insn, uint32_t val) goto bad_reg; } break; - case 14: /* Generic timer */ - if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) { - /* Dummy implementation: RAZ/WI for all */ - break; - } - goto bad_reg; case 15: /* Implementation specific. */ if (arm_feature(env, ARM_FEATURE_XSCALE)) { if (op2 == 0 && crm == 1) { @@ -2070,12 +2075,6 @@ uint32_t HELPER(get_cp15)(CPUARMState *env, uint32_t insn) default: goto bad_reg; } - case 14: /* Generic timer */ - if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) { - /* Dummy implementation: RAZ/WI for all */ - return 0; - } - goto bad_reg; case 15: /* Implementation specific. */ if (arm_feature(env, ARM_FEATURE_XSCALE)) { if (op2 == 0 && crm == 1)