From patchwork Wed May 2 17:12:11 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 8360 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 3E32523E37 for ; Wed, 2 May 2012 17:12:22 +0000 (UTC) Received: from mail-gy0-f180.google.com (mail-gy0-f180.google.com [209.85.160.180]) by fiordland.canonical.com (Postfix) with ESMTP id 0F6ACA1841B for ; Wed, 2 May 2012 17:12:21 +0000 (UTC) Received: by ghbz12 with SMTP id z12so1126491ghb.11 for ; Wed, 02 May 2012 10:12:21 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=edPuxj4vcRXEnsRsq8BizxI8FfSzvdk7CD+1ZoaYpnA=; b=Vy00D39cwvmUmJuFDZgLvdRLXNkfOkCcDx3n9BlQmUMnFZMOwddHTvjur0TSE4Raz2 ARcmzl3eLWOYbOuOLiONI7xVIJBi+OD/SJRHwkCtr0NwCJSz3aOqLef28AE8/uAla3El v0Dyx7aoi2+w912a2Kevuxt5p69G4Q30ULqCiIf/404X1uAaVaQ9EfZ0V4QA4maegSOy AIfmXB1aVPukyuXtzrP3KLX0/yRALQAmcMjLtG8TXaEl7sQ7PtLxf4jZ/WILQYR7ujdw gxNzjzU69rNeJEmSgjy2/XWX7Sd/0+KOj0N5sP6ENddzGnkbJqCBukM8dtnDrn03q22t sqOg== Received: by 10.42.122.76 with SMTP id m12mr2424379icr.38.1335978741365; Wed, 02 May 2012 10:12:21 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.137.198 with SMTP id x6csp267493ibt; Wed, 2 May 2012 10:12:17 -0700 (PDT) Received: by 10.216.138.135 with SMTP id a7mr18148367wej.19.1335978737089; Wed, 02 May 2012 10:12:17 -0700 (PDT) Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk. [81.2.115.146]) by mx.google.com with ESMTPS id m60si2752666wee.64.2012.05.02.10.12.15 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 02 May 2012 10:12:17 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) client-ip=81.2.115.146; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1SPd65-0008Ts-LA; Wed, 02 May 2012 18:12:13 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Paul Brook , =?UTF-8?q?Andreas=20F=C3=A4rber?= Subject: [PATCH 8/9] hw/arm_gic: Move CPU interface memory region setup into arm_gic_init Date: Wed, 2 May 2012 18:12:11 +0100 Message-Id: <1335978732-32559-9-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1335978732-32559-1-git-send-email-peter.maydell@linaro.org> References: <1335978732-32559-1-git-send-email-peter.maydell@linaro.org> X-Gm-Message-State: ALoCoQnLgtikKbbogxFeaFbSe3bilz2G2WQiDLN+h6BwlfXSEKr63d3SQtYHIFHwAs5YuiV5ZWJ1 Remove more NVIC ifdefs by moving the code to setup the CPU interface memory regions into the GIC specific arm_gic_init() function rather than the gic_init() function. Rename the latter to more closely reflect what it's now actually doing. Signed-off-by: Peter Maydell --- hw/arm_gic.c | 26 +++++++++++++------------- hw/armv7m_nvic.c | 2 +- 2 files changed, 14 insertions(+), 14 deletions(-) diff --git a/hw/arm_gic.c b/hw/arm_gic.c index c288bc5..ad5ab3c 100644 --- a/hw/arm_gic.c +++ b/hw/arm_gic.c @@ -812,7 +812,7 @@ static int gic_load(QEMUFile *f, void *opaque, int version_id) return 0; } -static void gic_init(gic_state *s, int num_irq) +static void gic_init_irqs_and_distributor(gic_state *s, int num_irq) { int i; @@ -850,7 +850,19 @@ static void gic_init(gic_state *s, int num_irq) sysbus_init_irq(&s->busdev, &s->parent_irq[i]); } memory_region_init_io(&s->iomem, &gic_dist_ops, s, "gic_dist", 0x1000); + + register_savevm(NULL, "arm_gic", -1, 3, gic_save, gic_load, s); +} + #ifndef NVIC + +static int arm_gic_init(SysBusDevice *dev) +{ + /* Device instance init function for the GIC sysbus device */ + int i; + gic_state *s = FROM_SYSBUS(gic_state, dev); + gic_init_irqs_and_distributor(s, s->num_irq); + /* Memory regions for the CPU interfaces (NVIC doesn't have these): * a region for "CPU interface for this core", then a region for * "CPU interface for core 0", "for core 1", ... @@ -866,19 +878,7 @@ static void gic_init(gic_state *s, int num_irq) memory_region_init_io(&s->cpuiomem[i+1], &gic_cpu_ops, &s->backref[i], "gic_cpu", 0x100); } -#endif - - register_savevm(NULL, "arm_gic", -1, 3, gic_save, gic_load, s); -} - -#ifndef NVIC -static int arm_gic_init(SysBusDevice *dev) -{ - /* Device instance init function for the GIC sysbus device */ - int i; - gic_state *s = FROM_SYSBUS(gic_state, dev); - gic_init(s, s->num_irq); /* Distributor */ sysbus_init_mmio(dev, &s->iomem); /* cpu interfaces (one for "current cpu" plus one per cpu) */ diff --git a/hw/armv7m_nvic.c b/hw/armv7m_nvic.c index 4c130f1..031a7fd 100644 --- a/hw/armv7m_nvic.c +++ b/hw/armv7m_nvic.c @@ -449,7 +449,7 @@ static int armv7m_nvic_init(SysBusDevice *dev) s->gic.num_cpu = 1; /* Tell the common code we're an NVIC */ s->gic.revision = 0xffffffff; - gic_init(&s->gic, s->num_irq); + gic_init_irqs_and_distributor(&s->gic, s->num_irq); /* The NVIC and system controller register area looks like this: * 0..0xff : system control registers, including systick * 0x100..0xcff : GIC-like registers