From patchwork Wed May 2 17:12:10 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 8363 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id DDE1023EC7 for ; Wed, 2 May 2012 17:12:28 +0000 (UTC) Received: from mail-gy0-f180.google.com (mail-gy0-f180.google.com [209.85.160.180]) by fiordland.canonical.com (Postfix) with ESMTP id A32D3A1874C for ; Wed, 2 May 2012 17:12:28 +0000 (UTC) Received: by mail-gy0-f180.google.com with SMTP id z12so1126491ghb.11 for ; Wed, 02 May 2012 10:12:28 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=WkjT/L5zYkbt4dW89/hP/tM3tGZ2PpCvOlWCoFRKrB0=; b=WmpJGoezI1tL+Ex9ef30gpp5UU3aSJslOsZngJjNh9MtiN4/u/57icMhG3mfdIj0yf R1hjRE9mVxBoAd/sRckavKJ1mm64yHygRdJglyFAbtF/OQ7MMCoR+u+fb2pr0UskkdQe xKkk10ZvtdmqK7IyJQw0+lXdNt+PKnuRdEjaOWMXQsj2sHff3CSGU5PCBCTIsmWPCHnJ hoEfKZiDeed9pQwihppZ0GuJmdFvMJULSILViFoA6dz0ETRISoxipfFvwXJxLnGVUDZJ /j3eKJ5DvFcLTm9jUHODdJl/ZwL/a+E9u1G68fCGcVZsNMakGOShYbhSBDoAd6PjVwHb u+2A== Received: by 10.50.51.163 with SMTP id l3mr5862038igo.3.1335978748327; Wed, 02 May 2012 10:12:28 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.137.198 with SMTP id x6csp267512ibt; Wed, 2 May 2012 10:12:26 -0700 (PDT) Received: by 10.180.97.4 with SMTP id dw4mr15875269wib.18.1335978745923; Wed, 02 May 2012 10:12:25 -0700 (PDT) Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk. [81.2.115.146]) by mx.google.com with ESMTPS id n9si2774515wed.21.2012.05.02.10.12.25 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 02 May 2012 10:12:25 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) client-ip=81.2.115.146; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1SPd65-0008Tq-It; Wed, 02 May 2012 18:12:13 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Paul Brook , =?UTF-8?q?Andreas=20F=C3=A4rber?= Subject: [PATCH 7/9] hw/arm_gic.c: Make NVIC interrupt numbering a runtime setting Date: Wed, 2 May 2012 18:12:10 +0100 Message-Id: <1335978732-32559-8-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1335978732-32559-1-git-send-email-peter.maydell@linaro.org> References: <1335978732-32559-1-git-send-email-peter.maydell@linaro.org> X-Gm-Message-State: ALoCoQkxiBNp8gmkUNqX2PSnp1IIOUYkf+swW2SX5WaoCUOrXU/IpT8jZgu1MmLRs1PFPhYtxDzC Make the minor tweaks to interrupt numbering used by the NVIC a runtime setting rather than a compile time one, so we can drop more NVIC ifdefs. Signed-off-by: Peter Maydell --- hw/arm_gic.c | 12 ++++-------- 1 files changed, 4 insertions(+), 8 deletions(-) diff --git a/hw/arm_gic.c b/hw/arm_gic.c index a6e2431..c288bc5 100644 --- a/hw/arm_gic.c +++ b/hw/arm_gic.c @@ -36,13 +36,9 @@ do { printf("arm_gic: " fmt , ## __VA_ARGS__); } while (0) #define DPRINTF(fmt, ...) do {} while(0) #endif -#ifdef NVIC /* The NVIC has 16 internal vectors. However these are not exposed through the normal GIC interface. */ -#define GIC_BASE_IRQ 32 -#else -#define GIC_BASE_IRQ 0 -#endif +#define GIC_BASE_IRQ ((s->revision == REV_NVIC) ? 32 : 0) static const uint8_t gic_id[] = { 0x90, 0x13, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 @@ -839,7 +835,6 @@ static void gic_init(gic_state *s, int num_irq) } i = s->num_irq - GIC_INTERNAL; -#ifndef NVIC /* For the GIC, also expose incoming GPIO lines for PPIs for each CPU. * GPIO array layout is thus: * [0..N-1] SPIs @@ -847,8 +842,9 @@ static void gic_init(gic_state *s, int num_irq) * [N+32..N+63] PPIs for CPU 1 * ... */ - i += (GIC_INTERNAL * s->num_cpu); -#endif + if (s->revision != REV_NVIC) { + i += (GIC_INTERNAL * s->num_cpu); + } qdev_init_gpio_in(&s->busdev.qdev, gic_set_irq, i); for (i = 0; i < NUM_CPU(s); i++) { sysbus_init_irq(&s->busdev, &s->parent_irq[i]);