From patchwork Wed May 2 17:12:09 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 8359 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 6D72023E37 for ; Wed, 2 May 2012 17:12:21 +0000 (UTC) Received: from mail-yw0-f52.google.com (mail-yw0-f52.google.com [209.85.213.52]) by fiordland.canonical.com (Postfix) with ESMTP id 21820A1841B for ; Wed, 2 May 2012 17:12:21 +0000 (UTC) Received: by yhpp61 with SMTP id p61so1132622yhp.11 for ; Wed, 02 May 2012 10:12:20 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=bW5RHMkd+r8/azxFwnnh9IUgPEnVW5zxZOpQGKUmKZ4=; b=EVrASi+oygyShFGLymkP/HcUNAKMdkzyKpXX7aODh1W8Lu6lM55qt+V6DqGsQn3fx5 HZpTrD9fKGsanwPG2r93Wa1GgHxRtVAMyRXmohbaXznRfCJqyf3rg0ebg1jr26xut5cp tPm56H1k8J4bhUm04bFkxME7hsty4giiZvNpkkB8jtJb6CLuysxeVTCz7jGEGf1fiMLg V/yg7Dt6PuZqwgb8iXXahOZDuXciE/JAHSgG2ocCkJLT7BARv1R+FGhJJlQkpIIlkNAi iYqHwKxXv9Y43X+r46rCN9cwwhd+2LdRDztoloKkTWVm/wPQ3hVlefQg2gkhU3WYSzeu vHeQ== Received: by 10.50.160.225 with SMTP id xn1mr5864576igb.3.1335978740265; Wed, 02 May 2012 10:12:20 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.137.198 with SMTP id x6csp267492ibt; Wed, 2 May 2012 10:12:17 -0700 (PDT) Received: by 10.204.130.85 with SMTP id r21mr2001731bks.53.1335978737130; Wed, 02 May 2012 10:12:17 -0700 (PDT) Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk. [81.2.115.146]) by mx.google.com with ESMTPS id tb1si848760bkb.19.2012.05.02.10.12.15 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 02 May 2012 10:12:17 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) client-ip=81.2.115.146; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1SPd65-0008To-Fe; Wed, 02 May 2012 18:12:13 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Paul Brook , =?UTF-8?q?Andreas=20F=C3=A4rber?= Subject: [PATCH 6/9] hw/arm_gic: Make CPU target registers RAZ/WI on uniprocessor Date: Wed, 2 May 2012 18:12:09 +0100 Message-Id: <1335978732-32559-7-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1335978732-32559-1-git-send-email-peter.maydell@linaro.org> References: <1335978732-32559-1-git-send-email-peter.maydell@linaro.org> X-Gm-Message-State: ALoCoQl2tVff/lailDwkWHH1Wnx/rHz3xfWEx18mzkRtE/goQPz1UTseDpIexn7IOxd7iqLvTxZF The GIC spec says that the CPU target registers should RAZ/WI for uniprocessor implementations. Implement this, which also conveniently lets us drop an NVIC ifdef. Annoyingly, the 11MPCore's GIC is the odd one out, since it always has these registers, even in uniprocessor configs. Signed-off-by: Peter Maydell --- hw/arm_gic.c | 56 +++++++++++++++++++++++++++++++++----------------------- 1 files changed, 33 insertions(+), 23 deletions(-) diff --git a/hw/arm_gic.c b/hw/arm_gic.c index ad72ac6..a6e2431 100644 --- a/hw/arm_gic.c +++ b/hw/arm_gic.c @@ -86,11 +86,7 @@ typedef struct gic_irq_state #define GIC_GET_PRIORITY(irq, cpu) (((irq) < GIC_INTERNAL) ? \ s->priority1[irq][cpu] : \ s->priority2[(irq) - GIC_INTERNAL]) -#ifdef NVIC -#define GIC_TARGET(irq) 1 -#else #define GIC_TARGET(irq) s->irq_target[irq] -#endif typedef struct gic_state { @@ -377,18 +373,22 @@ static uint32_t gic_dist_readb(void *opaque, target_phys_addr_t offset) if (irq >= s->num_irq) goto bad_reg; res = GIC_GET_PRIORITY(irq, cpu); -#ifndef NVIC } else if (offset < 0xc00) { /* Interrupt CPU Target. */ - irq = (offset - 0x800) + GIC_BASE_IRQ; - if (irq >= s->num_irq) - goto bad_reg; - if (irq >= 29 && irq <= 31) { - res = cm; + if (s->num_cpu == 1 && s->revision != REV_11MPCORE) { + /* For uniprocessor GICs these RAZ/WI */ + res = 0; } else { - res = GIC_TARGET(irq); + irq = (offset - 0x800) + GIC_BASE_IRQ; + if (irq >= s->num_irq) { + goto bad_reg; + } + if (irq >= 29 && irq <= 31) { + res = cm; + } else { + res = GIC_TARGET(irq); + } } -#endif } else if (offset < 0xf00) { /* Interrupt Configuration. */ irq = (offset - 0xc00) * 2 + GIC_BASE_IRQ; @@ -533,18 +533,22 @@ static void gic_dist_writeb(void *opaque, target_phys_addr_t offset, } else { s->priority2[irq - GIC_INTERNAL] = value; } -#ifndef NVIC } else if (offset < 0xc00) { - /* Interrupt CPU Target. */ - irq = (offset - 0x800) + GIC_BASE_IRQ; - if (irq >= s->num_irq) - goto bad_reg; - if (irq < 29) - value = 0; - else if (irq < GIC_INTERNAL) - value = ALL_CPU_MASK; - s->irq_target[irq] = value & ALL_CPU_MASK; -#endif + /* Interrupt CPU Target. RAZ/WI on uniprocessor GICs, with the + * annoying exception of the 11MPCore's GIC. + */ + if (s->num_cpu != 1 || s->revision == REV_11MPCORE) { + irq = (offset - 0x800) + GIC_BASE_IRQ; + if (irq >= s->num_irq) { + goto bad_reg; + } + if (irq < 29) { + value = 0; + } else if (irq < GIC_INTERNAL) { + value = ALL_CPU_MASK; + } + s->irq_target[irq] = value & ALL_CPU_MASK; + } } else if (offset < 0xf00) { /* Interrupt Configuration. */ irq = (offset - 0xc00) * 4 + GIC_BASE_IRQ; @@ -733,6 +737,12 @@ static void gic_reset(DeviceState *dev) GIC_SET_ENABLED(i, ALL_CPU_MASK); GIC_SET_TRIGGER(i); } + if (s->num_cpu == 1) { + /* For uniprocessor GICs all interrupts always target the sole CPU */ + for (i = 0; i < GIC_MAXIRQ; i++) { + s->irq_target[i] = 1; + } + } s->enabled = 0; }