From patchwork Wed May 2 17:12:08 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 8357 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id A168723E37 for ; Wed, 2 May 2012 17:12:19 +0000 (UTC) Received: from mail-yx0-f180.google.com (mail-yx0-f180.google.com [209.85.213.180]) by fiordland.canonical.com (Postfix) with ESMTP id 4C49AA1841B for ; Wed, 2 May 2012 17:12:19 +0000 (UTC) Received: by yenl4 with SMTP id l4so1117349yen.11 for ; Wed, 02 May 2012 10:12:18 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=ZTfU9+wTE8PoB7CPD1c7nXIOMzVNINeN7MY67yq3CRc=; b=L0VSkhXXtaOeXo+hMl4LetWfLiXMEgsifuP8oBNCSOiy8cpcxoeiMNZ9QaDqkXcS7w uryjxw3RsJtPq4KjffjNVVlv5KTdyEbdl6++EEjUWM5YPieRr5NgR2BpPo8gGnPkCs1Z hzss53DQXLpHrww+NpdTJJYmlQYqW0utauhUnR7BpBB5y+yrauauuYHUBxzLxAnwP7st 9CD9EPqSVVqkik1UhfF8Yh15s01+RCcpQSUQI/6QHMGVQp9si8p7B+wPQZ4NkbUK79dF EVitwaukbqA+/vUELuvLW9ULTbJZImzCvg8gz7tCXTTBD7gt7wWz9A3xNIQddBuOmMDe of8w== Received: by 10.50.89.168 with SMTP id bp8mr5860950igb.3.1335978738497; Wed, 02 May 2012 10:12:18 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.137.198 with SMTP id x6csp267490ibt; Wed, 2 May 2012 10:12:17 -0700 (PDT) Received: by 10.180.86.197 with SMTP id r5mr12234426wiz.21.1335978736954; Wed, 02 May 2012 10:12:16 -0700 (PDT) Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk. [81.2.115.146]) by mx.google.com with ESMTPS id m20si2733922wee.122.2012.05.02.10.12.15 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 02 May 2012 10:12:16 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) client-ip=81.2.115.146; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1SPd65-0008Tm-De; Wed, 02 May 2012 18:12:13 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Paul Brook , =?UTF-8?q?Andreas=20F=C3=A4rber?= Subject: [PATCH 5/9] hw/arm_gic: Add qdev property for GIC revision Date: Wed, 2 May 2012 18:12:08 +0100 Message-Id: <1335978732-32559-6-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1335978732-32559-1-git-send-email-peter.maydell@linaro.org> References: <1335978732-32559-1-git-send-email-peter.maydell@linaro.org> X-Gm-Message-State: ALoCoQkmOynzk+p8Zn8oeJ1qg8ELb512fYKqXWb1r1puRaa5Rnj7L6kDDLdchDADHWST8Y35cySS GIC behaviour can be different between revision 1 and 2 of the architectural GIC specification; we also have to handle the legacy 11MPCore GIC, which is different again in some places. Introduce a qdev property so we can behave appropriately. Signed-off-by: Peter Maydell --- hw/a15mpcore.c | 1 + hw/arm11mpcore.c | 2 ++ hw/arm_gic.c | 10 ++++++++++ hw/armv7m_nvic.c | 2 ++ 4 files changed, 15 insertions(+), 0 deletions(-) diff --git a/hw/a15mpcore.c b/hw/a15mpcore.c index 5a7b365..fc0a02a 100644 --- a/hw/a15mpcore.c +++ b/hw/a15mpcore.c @@ -44,6 +44,7 @@ static int a15mp_priv_init(SysBusDevice *dev) s->gic = qdev_create(NULL, "arm_gic"); qdev_prop_set_uint32(s->gic, "num-cpu", s->num_cpu); qdev_prop_set_uint32(s->gic, "num-irq", s->num_irq); + qdev_prop_set_uint32(s->gic, "revision", 2); qdev_init_nofail(s->gic); busdev = sysbus_from_qdev(s->gic); diff --git a/hw/arm11mpcore.c b/hw/arm11mpcore.c index c528d7a..1bff3d3 100644 --- a/hw/arm11mpcore.c +++ b/hw/arm11mpcore.c @@ -123,6 +123,8 @@ static int mpcore_priv_init(SysBusDevice *dev) s->gic = qdev_create(NULL, "arm_gic"); qdev_prop_set_uint32(s->gic, "num-cpu", s->num_cpu); qdev_prop_set_uint32(s->gic, "num-irq", s->num_irq); + /* Request the legacy 11MPCore GIC behaviour: */ + qdev_prop_set_uint32(s->gic, "revision", 0); qdev_init_nofail(s->gic); /* Pass through outbound IRQ lines from the GIC */ diff --git a/hw/arm_gic.c b/hw/arm_gic.c index 2ec10ce..ad72ac6 100644 --- a/hw/arm_gic.c +++ b/hw/arm_gic.c @@ -119,8 +119,13 @@ typedef struct gic_state struct gic_state *backref[NCPU]; MemoryRegion cpuiomem[NCPU+1]; /* CPU interfaces */ uint32_t num_irq; + uint32_t revision; } gic_state; +/* The special cases for the revision property: */ +#define REV_11MPCORE 0 +#define REV_NVIC 0xffffffff + static inline int gic_get_current_cpu(gic_state *s) { if (s->num_cpu > 1) { @@ -880,6 +885,11 @@ static int arm_gic_init(SysBusDevice *dev) static Property arm_gic_properties[] = { DEFINE_PROP_UINT32("num-cpu", gic_state, num_cpu, 1), DEFINE_PROP_UINT32("num-irq", gic_state, num_irq, 32), + /* Revision can be 1 or 2 for GIC architecture specification + * versions 1 or 2, or 0 to indicate the legacy 11MPCore GIC. + * (Internally, 0xffffffff also indicates "not a GIC but an NVIC".) + */ + DEFINE_PROP_UINT32("revision", gic_state, revision, 1), DEFINE_PROP_END_OF_LIST(), }; diff --git a/hw/armv7m_nvic.c b/hw/armv7m_nvic.c index 747e245..4c130f1 100644 --- a/hw/armv7m_nvic.c +++ b/hw/armv7m_nvic.c @@ -447,6 +447,8 @@ static int armv7m_nvic_init(SysBusDevice *dev) /* The NVIC always has only one CPU */ s->gic.num_cpu = 1; + /* Tell the common code we're an NVIC */ + s->gic.revision = 0xffffffff; gic_init(&s->gic, s->num_irq); /* The NVIC and system controller register area looks like this: * 0..0xff : system control registers, including systick