From patchwork Wed May 2 17:12:05 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 8358 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 31F7723E37 for ; Wed, 2 May 2012 17:12:20 +0000 (UTC) Received: from mail-yx0-f180.google.com (mail-yx0-f180.google.com [209.85.213.180]) by fiordland.canonical.com (Postfix) with ESMTP id 03203A1841B for ; Wed, 2 May 2012 17:12:19 +0000 (UTC) Received: by mail-yx0-f180.google.com with SMTP id l4so1117349yen.11 for ; Wed, 02 May 2012 10:12:19 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=8OhQempkpOsHQofUExYBB+O09R3l3mefbySraSuAyYs=; b=dcH0v4R5zCJccGWIqyBlV7O/O40ZEojxi/73YdrA7TkxP4TetZdLx3VYRwR0e9PT6+ 5N14Rfl1WKgtE4XtanHCDPVB0tKovHU6qlfkp+hG4kLKI2eZak1l2cbiIttHHf/wFG79 UMiDU0djHmhb4CN3LETQCDmhACWXnjmC0zKIPgfIu/iUMzmFkvNLfSjLwKjK5ePsuaF7 r5//8WZtfvNYdLOkf/sS/YTwoOVU8rYCwCA1kqt0XlGSgSlmqnRz2v8eHMwfqcJXlNd2 DRnp813su8xdOzCHlaj+/xk9fX7gCT27V25eeXyJbI0HdtQYISWSXpLiSOaGSULXZsZb RZ0g== Received: by 10.50.41.196 with SMTP id h4mr5967721igl.33.1335978739546; Wed, 02 May 2012 10:12:19 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.137.198 with SMTP id x6csp267491ibt; Wed, 2 May 2012 10:12:17 -0700 (PDT) Received: by 10.216.138.17 with SMTP id z17mr4098193wei.18.1335978736998; Wed, 02 May 2012 10:12:16 -0700 (PDT) Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk. [81.2.115.146]) by mx.google.com with ESMTPS id s1si22554151wia.9.2012.05.02.10.12.15 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 02 May 2012 10:12:16 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) client-ip=81.2.115.146; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1SPd65-0008Tg-5D; Wed, 02 May 2012 18:12:13 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Paul Brook , =?UTF-8?q?Andreas=20F=C3=A4rber?= Subject: [PATCH 2/9] hw/arm_gic: Remove the special casing of NCPU for the NVIC Date: Wed, 2 May 2012 18:12:05 +0100 Message-Id: <1335978732-32559-3-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1335978732-32559-1-git-send-email-peter.maydell@linaro.org> References: <1335978732-32559-1-git-send-email-peter.maydell@linaro.org> X-Gm-Message-State: ALoCoQlWGcSCp5wQ0ODcsI0c6LjNq1FP0GwK1yKojGB+Luyaep2A+SBHeHZPlZ66G2m8LiOgq5Qa Drop the special casing of NCPU=1 for the NVIC. This slightly increases the amount of memory used by its state structure, but removes some ifdeffery and means we can safely move the GIC state into a common subclass structure. Signed-off-by: Peter Maydell --- hw/arm_gic.c | 23 +++-------------------- hw/armv7m_nvic.c | 5 ++--- 2 files changed, 5 insertions(+), 23 deletions(-) diff --git a/hw/arm_gic.c b/hw/arm_gic.c index 17b2eba..2d8ceb8 100644 --- a/hw/arm_gic.c +++ b/hw/arm_gic.c @@ -25,11 +25,7 @@ /* First 32 are private to each CPU (SGIs and PPIs). */ #define GIC_INTERNAL 32 /* Maximum number of possible CPU interfaces, determined by GIC architecture */ -#ifdef NVIC -#define NCPU 1 -#else #define NCPU 8 -#endif //#define DEBUG_GIC @@ -67,11 +63,7 @@ typedef struct gic_irq_state } gic_irq_state; #define ALL_CPU_MASK ((unsigned)(((1 << NCPU) - 1))) -#if NCPU > 1 #define NUM_CPU(s) ((s)->num_cpu) -#else -#define NUM_CPU(s) 1 -#endif #define GIC_SET_ENABLED(irq, cm) s->irq_state[irq].enabled |= (cm) #define GIC_CLEAR_ENABLED(irq, cm) s->irq_state[irq].enabled &= ~(cm) @@ -131,11 +123,9 @@ typedef struct gic_state static inline int gic_get_current_cpu(gic_state *s) { -#if NCPU > 1 if (s->num_cpu > 1) { return cpu_single_env->cpu_index; } -#endif return 0; } @@ -842,21 +832,14 @@ static int gic_load(QEMUFile *f, void *opaque, int version_id) return 0; } -#if NCPU > 1 -static void gic_init(gic_state *s, int num_cpu, int num_irq) -#else static void gic_init(gic_state *s, int num_irq) -#endif { int i; -#if NCPU > 1 - s->num_cpu = num_cpu; if (s->num_cpu > NCPU) { hw_error("requested %u CPUs exceeds GIC maximum %d\n", - num_cpu, NCPU); + s->num_cpu, NCPU); } -#endif s->num_irq = num_irq + GIC_BASE_IRQ; if (s->num_irq > GIC_MAXIRQ) { hw_error("requested %u interrupt lines exceeds GIC maximum %d\n", @@ -880,7 +863,7 @@ static void gic_init(gic_state *s, int num_irq) * [N+32..N+63] PPIs for CPU 1 * ... */ - i += (GIC_INTERNAL * num_cpu); + i += (GIC_INTERNAL * s->num_cpu); #endif qdev_init_gpio_in(&s->busdev.qdev, gic_set_irq, i); for (i = 0; i < NUM_CPU(s); i++) { @@ -915,7 +898,7 @@ static int arm_gic_init(SysBusDevice *dev) /* Device instance init function for the GIC sysbus device */ int i; gic_state *s = FROM_SYSBUS(gic_state, dev); - gic_init(s, s->num_cpu, s->num_irq); + gic_init(s, s->num_irq); /* Distributor */ sysbus_init_mmio(dev, &s->iomem); /* cpu interfaces (one for "current cpu" plus one per cpu) */ diff --git a/hw/armv7m_nvic.c b/hw/armv7m_nvic.c index 986a6bb..99a87a2 100644 --- a/hw/armv7m_nvic.c +++ b/hw/armv7m_nvic.c @@ -389,9 +389,8 @@ static int armv7m_nvic_init(SysBusDevice *dev) { nvic_state *s= FROM_SYSBUSGIC(nvic_state, dev); - /* note that for the M profile gic_init() takes the number of external - * interrupt lines only. - */ + /* The NVIC always has only one CPU */ + s->gic.num_cpu = 1; gic_init(&s->gic, s->num_irq); memory_region_add_subregion(get_system_memory(), 0xe000e000, &s->gic.iomem); s->systick.timer = qemu_new_timer_ns(vm_clock, systick_timer_tick, s);