From patchwork Sun Apr 15 13:45:58 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 7851 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 75D4C23E47 for ; Sun, 15 Apr 2012 13:46:48 +0000 (UTC) Received: from mail-iy0-f180.google.com (mail-iy0-f180.google.com [209.85.210.180]) by fiordland.canonical.com (Postfix) with ESMTP id 3E7DDA181A5 for ; Sun, 15 Apr 2012 13:46:48 +0000 (UTC) Received: by mail-iy0-f180.google.com with SMTP id e36so8543085iag.11 for ; Sun, 15 Apr 2012 06:46:48 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=PFyP5NW0DbkLdw0bN/gsvCZOVmPBU5pL12ZZ4Dtp9vo=; b=ccXD0A1FsX0deiv32CJBtUbrk+VRpGXyetccmddxq7c8Xq/y9bFAlNejlNJecNJ4ao DyuOAuRzJ3BP9hzHMeXWLDtC4Y4EXtfD9BtiatBpr5+dMF9wk6DAGYL/AgWefUTYy8TH xKspmiU65yVbyl62kFLB8BlSRcYwePXt0z5qw5xuh7xfMr4obFCDeKv4XWHGm2cWLeuB 5ihixnHXEjbspPxC8XwvDb/Th8iCqK3ziYhEIk9RwIMGDYvTPbHqfLmU7Ddekic4MIJk z6bN+qEFSK/nuE2JznIWu5x/UVc9eKWKdCP+zkIWP7LlVV2C40+MmyO8aXWTUyylLG4P +FCg== Received: by 10.50.34.200 with SMTP id b8mr3113131igj.50.1334497608009; Sun, 15 Apr 2012 06:46:48 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.70.69 with SMTP id c5csp22243ibj; Sun, 15 Apr 2012 06:46:47 -0700 (PDT) Received: by 10.180.24.35 with SMTP id r3mr10832223wif.7.1334497606971; Sun, 15 Apr 2012 06:46:46 -0700 (PDT) Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk. [81.2.115.146]) by mx.google.com with ESMTPS id ei5si4825303wid.4.2012.04.15.06.46.46 (version=TLSv1/SSLv3 cipher=OTHER); Sun, 15 Apr 2012 06:46:46 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) client-ip=81.2.115.146; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1SJPmc-0000Ef-7H; Sun, 15 Apr 2012 14:46:26 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, =?UTF-8?q?Andreas=20F=C3=A4rber?= , Paul Brook Subject: [PATCH 05/32] target-arm: Remove old cpu_arm_set_cp_io infrastructure Date: Sun, 15 Apr 2012 14:45:58 +0100 Message-Id: <1334497585-867-6-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1334497585-867-1-git-send-email-peter.maydell@linaro.org> References: <1334497585-867-1-git-send-email-peter.maydell@linaro.org> X-Gm-Message-State: ALoCoQn3zY1w5kM76Mo4a2ucP+6LtUYyiT1g6FCBLhrE4o8T5sc+92U1YNE0bPH1pxo4T1VA6Dbt All the users of cpu_arm_set_cp_io have been converted, so we can remove it and the infrastructure it used. Signed-off-by: Peter Maydell --- target-arm/cpu.h | 10 -------- target-arm/helper.c | 54 ------------------------------------------------ target-arm/helper.h | 3 -- target-arm/translate.c | 41 +----------------------------------- 4 files changed, 1 insertions(+), 107 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index f35d24f..c23c760 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -231,12 +231,6 @@ typedef struct CPUARMState { /* Coprocessor information */ GHashTable *cp_regs; - /* Coprocessor IO used by peripherals */ - struct { - ARMReadCPFunc *cp_read; - ARMWriteCPFunc *cp_write; - void *opaque; - } cp[15]; void *nvic; const struct arm_boot_info *boot_info; } CPUARMState; @@ -403,10 +397,6 @@ void armv7m_nvic_set_pending(void *opaque, int irq); int armv7m_nvic_acknowledge_irq(void *opaque); void armv7m_nvic_complete_irq(void *opaque, int irq); -void cpu_arm_set_cp_io(CPUARMState *env, int cpnum, - ARMReadCPFunc *cp_read, ARMWriteCPFunc *cp_write, - void *opaque); - /* Interface for defining coprocessor registers. * Registers are defined in tables of arm_cp_reginfo structs * which are passed to define_arm_cp_regs(). diff --git a/target-arm/helper.c b/target-arm/helper.c index f054fca..60473fc 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -373,21 +373,6 @@ int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address, int rw, return 1; } -/* These should probably raise undefined insn exceptions. */ -void HELPER(set_cp)(CPUARMState *env, uint32_t insn, uint32_t val) -{ - int op1 = (insn >> 8) & 0xf; - cpu_abort(env, "cp%i insn %08x\n", op1, insn); - return; -} - -uint32_t HELPER(get_cp)(CPUARMState *env, uint32_t insn) -{ - int op1 = (insn >> 8) & 0xf; - cpu_abort(env, "cp%i insn %08x\n", op1, insn); - return 0; -} - void HELPER(set_cp15)(CPUARMState *env, uint32_t insn, uint32_t val) { cpu_abort(env, "cp15 insn %08x\n", insn); @@ -1124,31 +1109,6 @@ target_phys_addr_t cpu_get_phys_page_debug(CPUARMState *env, target_ulong addr) return phys_addr; } -void HELPER(set_cp)(CPUARMState *env, uint32_t insn, uint32_t val) -{ - int cp_num = (insn >> 8) & 0xf; - int cp_info = (insn >> 5) & 7; - int src = (insn >> 16) & 0xf; - int operand = insn & 0xf; - - if (env->cp[cp_num].cp_write) - env->cp[cp_num].cp_write(env->cp[cp_num].opaque, - cp_info, src, operand, val); -} - -uint32_t HELPER(get_cp)(CPUARMState *env, uint32_t insn) -{ - int cp_num = (insn >> 8) & 0xf; - int cp_info = (insn >> 5) & 7; - int dest = (insn >> 16) & 0xf; - int operand = insn & 0xf; - - if (env->cp[cp_num].cp_read) - return env->cp[cp_num].cp_read(env->cp[cp_num].opaque, - cp_info, dest, operand); - return 0; -} - /* Return basic MPU access permission bits. */ static uint32_t simple_mpu_ap_bits(uint32_t val) { @@ -2112,20 +2072,6 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val) } } -void cpu_arm_set_cp_io(CPUARMState *env, int cpnum, - ARMReadCPFunc *cp_read, ARMWriteCPFunc *cp_write, - void *opaque) -{ - if (cpnum < 0 || cpnum > 14) { - cpu_abort(env, "Bad coprocessor number: %i\n", cpnum); - return; - } - - env->cp[cpnum].cp_read = cp_read; - env->cp[cpnum].cp_write = cp_write; - env->cp[cpnum].opaque = opaque; -} - #endif /* Note that signed overflow is undefined in C. The following routines are diff --git a/target-arm/helper.h b/target-arm/helper.h index b6cefed..bb6b85d 100644 --- a/target-arm/helper.h +++ b/target-arm/helper.h @@ -62,9 +62,6 @@ DEF_HELPER_2(v7m_mrs, i32, env, i32) DEF_HELPER_3(set_cp15, void, env, i32, i32) DEF_HELPER_2(get_cp15, i32, env, i32) -DEF_HELPER_3(set_cp, void, env, i32, i32) -DEF_HELPER_2(get_cp, i32, env, i32) - DEF_HELPER_3(set_cp_reg, void, env, ptr, i32) DEF_HELPER_2(get_cp_reg, i32, env, ptr) DEF_HELPER_3(set_cp_reg64, void, env, ptr, i64) diff --git a/target-arm/translate.c b/target-arm/translate.c index ebb547e..a0cfbaa 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -2439,39 +2439,6 @@ static int disas_dsp_insn(CPUARMState *env, DisasContext *s, uint32_t insn) return 1; } -/* Disassemble system coprocessor instruction. Return nonzero if - instruction is not defined. */ -static int disas_cp_insn(CPUARMState *env, DisasContext *s, uint32_t insn) -{ - TCGv tmp, tmp2; - uint32_t rd = (insn >> 12) & 0xf; - uint32_t cp = (insn >> 8) & 0xf; - if (IS_USER(s)) { - return 1; - } - - if (insn & ARM_CP_RW_BIT) { - if (!env->cp[cp].cp_read) - return 1; - gen_set_pc_im(s->pc); - tmp = tcg_temp_new_i32(); - tmp2 = tcg_const_i32(insn); - gen_helper_get_cp(tmp, cpu_env, tmp2); - tcg_temp_free(tmp2); - store_reg(s, rd, tmp); - } else { - if (!env->cp[cp].cp_write) - return 1; - gen_set_pc_im(s->pc); - tmp = load_reg(s, rd); - tmp2 = tcg_const_i32(insn); - gen_helper_set_cp(cpu_env, tmp2, tmp); - tcg_temp_free(tmp2); - tcg_temp_free_i32(tmp); - } - return 0; -} - static int cp15_user_ok(CPUARMState *env, uint32_t insn) { int cpn = (insn >> 16) & 0xf; @@ -6652,10 +6619,6 @@ static int disas_coproc_insn(CPUARMState * env, DisasContext *s, uint32_t insn) */ switch (cpnum) { case 14: - /* Coprocessors 7-15 are architecturally reserved by ARM. - Unfortunately Intel decided to ignore this. */ - if (arm_feature(env, ARM_FEATURE_XSCALE)) - goto board; if (insn & (1 << 20)) return disas_cp14_read(env, s, insn); else @@ -6663,9 +6626,7 @@ static int disas_coproc_insn(CPUARMState * env, DisasContext *s, uint32_t insn) case 15: return disas_cp15_insn (env, s, insn); default: - board: - /* Unknown coprocessor. See if the board has hooked it. */ - return disas_cp_insn (env, s, insn); + return 1; } }