From patchwork Sun Apr 15 13:45:57 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 7836 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id E818F23E5C for ; Sun, 15 Apr 2012 13:46:34 +0000 (UTC) Received: from mail-iy0-f180.google.com (mail-iy0-f180.google.com [209.85.210.180]) by fiordland.canonical.com (Postfix) with ESMTP id A1AE1A181A5 for ; Sun, 15 Apr 2012 13:46:34 +0000 (UTC) Received: by iage36 with SMTP id e36so8543085iag.11 for ; Sun, 15 Apr 2012 06:46:34 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=ypIof9XqcxmeaLHf34dZTr1eR/Dkpvz6U+RLJiJcRMs=; b=WL2pa+D0NgWMxKqLUycusm7Nuw15KIGjQjRX8Mah1qvxXXG8+o10oYAPjGr5+TzivZ SbLFvh1tohQRFJBfGNWt17vLtjVucRZgfWLxdD5TF6bAMF9X/iz1Bo5/ebyNQ31BOMj7 Bz90VXvkCJplm4+o2Zh546N5Uhwz/5zbfbZcOS/OHSPF3S3aI7It2rMggxvlceaP3vom Ch2KgRvhSvzLx6rP708RRUKoothoNM8LPBDw47alGLwPNu+YseP/Tg1kYBYxFlsYwMPW slwJKDfeqTas2u7le0wkmTisSFSx8Tjb1RwwkTf5WV+3ph+qnNa+5pFdcTSta9mpP2GQ BRsw== Received: by 10.50.34.200 with SMTP id b8mr3112780igj.50.1334497594123; Sun, 15 Apr 2012 06:46:34 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.70.69 with SMTP id c5csp22197ibj; Sun, 15 Apr 2012 06:46:32 -0700 (PDT) Received: by 10.180.95.34 with SMTP id dh2mr10813868wib.15.1334497591742; Sun, 15 Apr 2012 06:46:31 -0700 (PDT) Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk. [81.2.115.146]) by mx.google.com with ESMTPS id c21si15299943wed.127.2012.04.15.06.46.30 (version=TLSv1/SSLv3 cipher=OTHER); Sun, 15 Apr 2012 06:46:31 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) client-ip=81.2.115.146; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1SJPmc-0000Ed-5G; Sun, 15 Apr 2012 14:46:26 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, =?UTF-8?q?Andreas=20F=C3=A4rber?= , Paul Brook Subject: [PATCH 04/32] hw/pxa2xx_pic: Convert coprocessor registers to new scheme Date: Sun, 15 Apr 2012 14:45:57 +0100 Message-Id: <1334497585-867-5-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1334497585-867-1-git-send-email-peter.maydell@linaro.org> References: <1334497585-867-1-git-send-email-peter.maydell@linaro.org> X-Gm-Message-State: ALoCoQmm8vpv1K3uO83mljuDFa8Wd+2qnklzl0RhZm5TBnfnq73aIYb+xIYJnDi9rJrWmErw+Kbk Convert the coprocessor access functions for the pxa2xx PIC to the arm_cp_reginfo scheme. Signed-off-by: Peter Maydell --- hw/pxa2xx_pic.c | 53 +++++++++++++++++++++++++++++++---------------------- 1 files changed, 31 insertions(+), 22 deletions(-) diff --git a/hw/pxa2xx_pic.c b/hw/pxa2xx_pic.c index a806b80..04c4d88 100644 --- a/hw/pxa2xx_pic.c +++ b/hw/pxa2xx_pic.c @@ -206,33 +206,42 @@ static const int pxa2xx_cp_reg_map[0x10] = { [0xa] = ICPR2, }; -static uint32_t pxa2xx_pic_cp_read(void *opaque, int op2, int reg, int crm) +static int pxa2xx_pic_cp_read(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t *value) { - target_phys_addr_t offset; - - if (pxa2xx_cp_reg_map[reg] == -1) { - printf("%s: Bad register 0x%x\n", __FUNCTION__, reg); - return 0; - } - - offset = pxa2xx_cp_reg_map[reg]; - return pxa2xx_pic_mem_read(opaque, offset, 4); + int offset = pxa2xx_cp_reg_map[ri->crn]; + *value = pxa2xx_pic_mem_read(ri->opaque, offset, 4); + return 0; } -static void pxa2xx_pic_cp_write(void *opaque, int op2, int reg, int crm, - uint32_t value) +static int pxa2xx_pic_cp_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) { - target_phys_addr_t offset; - - if (pxa2xx_cp_reg_map[reg] == -1) { - printf("%s: Bad register 0x%x\n", __FUNCTION__, reg); - return; - } - - offset = pxa2xx_cp_reg_map[reg]; - pxa2xx_pic_mem_write(opaque, offset, value, 4); + int offset = pxa2xx_cp_reg_map[ri->crn]; + pxa2xx_pic_mem_write(ri->opaque, offset, value, 4); + return 0; } +#define REGINFO_FOR_PIC_CP(NAME, CRN) \ + { .name = NAME, .cp = 6, .crn = CRN, .crm = 0, .opc1 = 0, .opc2 = 0, \ + .access = PL1_RW, \ + .readfn = pxa2xx_pic_cp_read, .writefn = pxa2xx_pic_cp_write } + +static const ARMCPRegInfo pxa_pic_cp_reginfo[] = { + REGINFO_FOR_PIC_CP("ICIP", 0), + REGINFO_FOR_PIC_CP("ICMR", 1), + REGINFO_FOR_PIC_CP("ICLR", 2), + REGINFO_FOR_PIC_CP("ICFP", 3), + REGINFO_FOR_PIC_CP("ICPR", 4), + REGINFO_FOR_PIC_CP("ICHP", 5), + REGINFO_FOR_PIC_CP("ICIP2", 6), + REGINFO_FOR_PIC_CP("ICMR2", 7), + REGINFO_FOR_PIC_CP("ICLR2", 8), + REGINFO_FOR_PIC_CP("ICFP2", 9), + REGINFO_FOR_PIC_CP("ICPR2", 0xa), + REGINFO_SENTINEL +}; + static const MemoryRegionOps pxa2xx_pic_ops = { .read = pxa2xx_pic_mem_read, .write = pxa2xx_pic_mem_write, @@ -270,7 +279,7 @@ DeviceState *pxa2xx_pic_init(target_phys_addr_t base, CPUARMState *env) sysbus_mmio_map(sysbus_from_qdev(dev), 0, base); /* Enable IC coprocessor access. */ - cpu_arm_set_cp_io(env, 6, pxa2xx_pic_cp_read, pxa2xx_pic_cp_write, s); + define_arm_cp_regs_with_opaque(env, pxa_pic_cp_reginfo, s); return dev; }