From patchwork Sun Apr 15 13:45:56 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 7860 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 2495123E47 for ; Sun, 15 Apr 2012 13:46:58 +0000 (UTC) Received: from mail-iy0-f180.google.com (mail-iy0-f180.google.com [209.85.210.180]) by fiordland.canonical.com (Postfix) with ESMTP id DDF82A181A5 for ; Sun, 15 Apr 2012 13:46:57 +0000 (UTC) Received: by mail-iy0-f180.google.com with SMTP id e36so8543068iag.11 for ; Sun, 15 Apr 2012 06:46:57 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=0P3iYCMjp+fhUjYrPSL8tn04jg/ZihTC4OGHH/NPd3g=; b=BjVSp+Jcy/e5douvjsfRJZY1r8hI5+3o9Nzj8R4HY1hd+R3Pz5C1gKlgqO4pD/LLGZ 0r3BIOMF3JAVPBe+pYlMUocZtSEK/16moPdBDM5sX4Re9TF7kv9lwgKTAUBP/Nbt6dKE nW3N2EwKjdcaa/swWt1tWEa7ARw5+GG9EnLVQwrm9bJZ8F2CZQvL/kMRnEvDvLOkoj3Z jZNKaccG/0dimn3qD6Y+QtNQKRhYeTbv82o9SaDaK/hC/BatgRAGLNk8y7lIgDRtJywv u4FTG92x83ter/Or9xeHnda2uooOVKJtRDzyzz8IEDnNA1AXo4Ez/ZOa7SYQFd2/ZXai Urcg== Received: by 10.42.152.134 with SMTP id i6mr4887217icw.27.1334497617661; Sun, 15 Apr 2012 06:46:57 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.70.69 with SMTP id c5csp22270ibj; Sun, 15 Apr 2012 06:46:57 -0700 (PDT) Received: by 10.204.133.212 with SMTP id g20mr2484200bkt.71.1334497616183; Sun, 15 Apr 2012 06:46:56 -0700 (PDT) Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk. [81.2.115.146]) by mx.google.com with ESMTPS id m5si5729724bke.12.2012.04.15.06.46.54 (version=TLSv1/SSLv3 cipher=OTHER); Sun, 15 Apr 2012 06:46:56 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) client-ip=81.2.115.146; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1SJPmc-0000Eb-3W; Sun, 15 Apr 2012 14:46:26 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, =?UTF-8?q?Andreas=20F=C3=A4rber?= , Paul Brook Subject: [PATCH 03/32] hw/pxa2xx.c: Convert CLKCFG and PWRMODE cp14 regs Date: Sun, 15 Apr 2012 14:45:56 +0100 Message-Id: <1334497585-867-4-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1334497585-867-1-git-send-email-peter.maydell@linaro.org> References: <1334497585-867-1-git-send-email-peter.maydell@linaro.org> X-Gm-Message-State: ALoCoQkkh8wX41AP/bH6lQWd+1+4Nbb9H7IilYxnU0SeoQwvFwIaYK0J7dmQePNEfp2rD4oYuGax Convert the PXA2xx CLKCFG and PWRMODE cp14 registers to the new arm_cp_reginfo scheme. Signed-off-by: Peter Maydell --- hw/pxa2xx.c | 171 ++++++++++++++++++++++++---------------------------------- 1 files changed, 71 insertions(+), 100 deletions(-) diff --git a/hw/pxa2xx.c b/hw/pxa2xx.c index 38d5b0e..c321bf3 100644 --- a/hw/pxa2xx.c +++ b/hw/pxa2xx.c @@ -224,131 +224,96 @@ static const VMStateDescription vmstate_pxa2xx_cm = { } }; -static uint32_t pxa2xx_clkpwr_read(void *opaque, int op2, int reg, int crm) +static int pxa2xx_clkcfg_read(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t *value) { - PXA2xxState *s = (PXA2xxState *) opaque; - - switch (reg) { - case 6: /* Clock Configuration register */ - return s->clkcfg; - - case 7: /* Power Mode register */ - return 0; + PXA2xxState *s = (PXA2xxState *)ri->opaque; + *value = s->clkcfg; + return 0; +} - default: - printf("%s: Bad register 0x%x\n", __FUNCTION__, reg); - break; +static int pxa2xx_clkcfg_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + PXA2xxState *s = (PXA2xxState *)ri->opaque; + s->clkcfg = value & 0xf; + if (value & 2) { + printf("%s: CPU frequency change attempt\n", __func__); } return 0; } -static void pxa2xx_clkpwr_write(void *opaque, int op2, int reg, int crm, - uint32_t value) +static int pxa2xx_pwrmode_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) { - PXA2xxState *s = (PXA2xxState *) opaque; + PXA2xxState *s = (PXA2xxState *)ri->opaque; static const char *pwrmode[8] = { "Normal", "Idle", "Deep-idle", "Standby", "Sleep", "reserved (!)", "reserved (!)", "Deep-sleep", }; - switch (reg) { - case 6: /* Clock Configuration register */ - s->clkcfg = value & 0xf; - if (value & 2) - printf("%s: CPU frequency change attempt\n", __FUNCTION__); + if (value & 8) { + printf("%s: CPU voltage change attempt\n", __func__); + } + switch (value & 7) { + case 0: + /* Do nothing */ break; - case 7: /* Power Mode register */ - if (value & 8) - printf("%s: CPU voltage change attempt\n", __FUNCTION__); - switch (value & 7) { - case 0: - /* Do nothing */ - break; - - case 1: - /* Idle */ - if (!(s->cm_regs[CCCR >> 2] & (1 << 31))) { /* CPDIS */ - cpu_interrupt(s->env, CPU_INTERRUPT_HALT); - break; - } - /* Fall through. */ - - case 2: - /* Deep-Idle */ + case 1: + /* Idle */ + if (!(s->cm_regs[CCCR >> 2] & (1 << 31))) { /* CPDIS */ cpu_interrupt(s->env, CPU_INTERRUPT_HALT); - s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */ - goto message; - - case 3: - s->env->uncached_cpsr = - ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I; - s->env->cp15.c1_sys = 0; - s->env->cp15.c1_coproc = 0; - s->env->cp15.c2_base0 = 0; - s->env->cp15.c3 = 0; - s->pm_regs[PSSR >> 2] |= 0x8; /* Set STS */ - s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */ - - /* - * The scratch-pad register is almost universally used - * for storing the return address on suspend. For the - * lack of a resuming bootloader, perform a jump - * directly to that address. - */ - memset(s->env->regs, 0, 4 * 15); - s->env->regs[15] = s->pm_regs[PSPR >> 2]; + break; + } + /* Fall through. */ + + case 2: + /* Deep-Idle */ + cpu_interrupt(s->env, CPU_INTERRUPT_HALT); + s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */ + goto message; + + case 3: + s->env->uncached_cpsr = + ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I; + s->env->cp15.c1_sys = 0; + s->env->cp15.c1_coproc = 0; + s->env->cp15.c2_base0 = 0; + s->env->cp15.c3 = 0; + s->pm_regs[PSSR >> 2] |= 0x8; /* Set STS */ + s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */ + + /* + * The scratch-pad register is almost universally used + * for storing the return address on suspend. For the + * lack of a resuming bootloader, perform a jump + * directly to that address. + */ + memset(s->env->regs, 0, 4 * 15); + s->env->regs[15] = s->pm_regs[PSPR >> 2]; #if 0 - buffer = 0xe59ff000; /* ldr pc, [pc, #0] */ - cpu_physical_memory_write(0, &buffer, 4); - buffer = s->pm_regs[PSPR >> 2]; - cpu_physical_memory_write(8, &buffer, 4); + buffer = 0xe59ff000; /* ldr pc, [pc, #0] */ + cpu_physical_memory_write(0, &buffer, 4); + buffer = s->pm_regs[PSPR >> 2]; + cpu_physical_memory_write(8, &buffer, 4); #endif - /* Suspend */ - cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT); - - goto message; + /* Suspend */ + cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT); - default: - message: - printf("%s: machine entered %s mode\n", __FUNCTION__, - pwrmode[value & 7]); - } - break; + goto message; default: - printf("%s: Bad register 0x%x\n", __FUNCTION__, reg); - break; + message: + printf("%s: machine entered %s mode\n", __func__, + pwrmode[value & 7]); } -} -static uint32_t pxa2xx_cp14_read(void *opaque, int op2, int reg, int crm) -{ - switch (crm) { - case 0: - return pxa2xx_clkpwr_read(opaque, op2, reg, crm); - default: - printf("%s: Bad register 0x%x\n", __FUNCTION__, reg); - break; - } return 0; } -static void pxa2xx_cp14_write(void *opaque, int op2, int reg, int crm, - uint32_t value) -{ - switch (crm) { - case 0: - pxa2xx_clkpwr_write(opaque, op2, reg, crm, value); - break; - default: - printf("%s: Bad register 0x%x\n", __FUNCTION__, reg); - break; - } -} - static int pxa2xx_cppmnc_read(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t *value) { @@ -400,6 +365,14 @@ static const ARMCPRegInfo pxa_cp_reginfo[] = { .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, { .name = "CPPMN3", .cp = 14, .crn = 2, .crm = 3, .opc1 = 0, .opc2 = 0, .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, + /* cp14 crn==6: CLKCFG */ + { .name = "CLKCFG", .cp = 14, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0, + .access = PL1_RW, + .readfn = pxa2xx_clkcfg_read, .writefn = pxa2xx_clkcfg_write }, + /* cp14 crn==7: PWRMODE */ + { .name = "PWRMODE", .cp = 14, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 0, + .access = PL1_RW, + .readfn = arm_cp_read_zero, .writefn = pxa2xx_pwrmode_write }, REGINFO_SENTINEL }; @@ -2111,7 +2084,6 @@ PXA2xxState *pxa270_init(MemoryRegion *address_space, memory_region_add_subregion(address_space, s->cm_base, &s->cm_iomem); vmstate_register(NULL, 0, &vmstate_pxa2xx_cm, s); - cpu_arm_set_cp_io(s->env, 14, pxa2xx_cp14_read, pxa2xx_cp14_write, s); pxa2xx_setup_cp14(s); s->mm_base = 0x48000000; @@ -2243,7 +2215,6 @@ PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size) memory_region_add_subregion(address_space, s->cm_base, &s->cm_iomem); vmstate_register(NULL, 0, &vmstate_pxa2xx_cm, s); - cpu_arm_set_cp_io(s->env, 14, pxa2xx_cp14_read, pxa2xx_cp14_write, s); pxa2xx_setup_cp14(s); s->mm_base = 0x48000000;