From patchwork Sun Apr 15 13:46:24 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 7854 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 27FFA23E47 for ; Sun, 15 Apr 2012 13:46:52 +0000 (UTC) Received: from mail-iy0-f180.google.com (mail-iy0-f180.google.com [209.85.210.180]) by fiordland.canonical.com (Postfix) with ESMTP id E1B81A181A5 for ; Sun, 15 Apr 2012 13:46:51 +0000 (UTC) Received: by mail-iy0-f180.google.com with SMTP id e36so8543068iag.11 for ; Sun, 15 Apr 2012 06:46:51 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=LhD7I06aR2Hj1b6PslYd/ByUoIAhAJJVOKmXDnq1kHY=; b=Al8h8ZodKYMOWmCP4NmClKPEPJ4C8AGm11XoUEpTlOls4SC1uSe0235ElXXcudhTpx U26TtI5BR7xqOiI7zvmpzqJJmcjHB386yA/a7WHqh0ZDmKr9/ysteLQfctVtg7DdEhjN gjNFbtcYVMePIWO+z3OU5Y4zKC1zofqItxskhldtltXOmk96G33X0BqXpGhhQGZJKx9Y TtaJIb2sx8s2oAW7rK7QLbgea7wbBNTiW5qjV5C0YIO/PdsByOa4xeenasbcQXnI3Hmb zmugT1uLJlg6ZqeGdkDMG/X/Xk2lR+1BmzKi7TZSVh52tj6R19GpsuH1zuoou/mqNvQ5 Hdmw== Received: by 10.50.158.202 with SMTP id ww10mr3052803igb.30.1334497611658; Sun, 15 Apr 2012 06:46:51 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.70.69 with SMTP id c5csp22249ibj; Sun, 15 Apr 2012 06:46:50 -0700 (PDT) Received: by 10.180.89.9 with SMTP id bk9mr10795458wib.11.1334497609998; Sun, 15 Apr 2012 06:46:49 -0700 (PDT) Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk. [81.2.115.146]) by mx.google.com with ESMTPS id x65si15321630weq.85.2012.04.15.06.46.49 (version=TLSv1/SSLv3 cipher=OTHER); Sun, 15 Apr 2012 06:46:49 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) client-ip=81.2.115.146; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1SJPme-0000FV-2A; Sun, 15 Apr 2012 14:46:28 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, =?UTF-8?q?Andreas=20F=C3=A4rber?= , Paul Brook Subject: [PATCH 31/32] target-arm: Remove remaining old cp15 infrastructure Date: Sun, 15 Apr 2012 14:46:24 +0100 Message-Id: <1334497585-867-32-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1334497585-867-1-git-send-email-peter.maydell@linaro.org> References: <1334497585-867-1-git-send-email-peter.maydell@linaro.org> X-Gm-Message-State: ALoCoQn56aoA6i9CPL2exAuBPW1dN+CatqwO1P2zTnlNlYb8Azm2cG7KdRKe0tVtMnsQrVQtxX55 There are now no uses of the old cp15 infrastructure, so it can be deleted. Signed-off-by: Peter Maydell --- target-arm/helper.c | 39 ------------------------------- target-arm/helper.h | 3 -- target-arm/translate.c | 59 +----------------------------------------------- 3 files changed, 1 insertions(+), 100 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index aef2e26..3c5671d 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -1422,16 +1422,6 @@ int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address, int rw, return 1; } -void HELPER(set_cp15)(CPUARMState *env, uint32_t insn, uint32_t val) -{ - cpu_abort(env, "cp15 insn %08x\n", insn); -} - -uint32_t HELPER(get_cp15)(CPUARMState *env, uint32_t insn) -{ - cpu_abort(env, "cp15 insn %08x\n", insn); -} - /* These should probably raise undefined insn exceptions. */ void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val) { @@ -2158,35 +2148,6 @@ target_phys_addr_t cpu_get_phys_page_debug(CPUARMState *env, target_ulong addr) return phys_addr; } -void HELPER(set_cp15)(CPUARMState *env, uint32_t insn, uint32_t val) -{ - int op1; - int op2; - int crm; - - op1 = (insn >> 21) & 7; - op2 = (insn >> 5) & 7; - crm = insn & 0xf; - /* ??? For debugging only. Should raise illegal instruction exception. */ - cpu_abort(env, "Unimplemented cp15 register write (c%d, c%d, {%d, %d})\n", - (insn >> 16) & 0xf, crm, op1, op2); -} - -uint32_t HELPER(get_cp15)(CPUARMState *env, uint32_t insn) -{ - int op1; - int op2; - int crm; - - op1 = (insn >> 21) & 7; - op2 = (insn >> 5) & 7; - crm = insn & 0xf; - /* ??? For debugging only. Should raise illegal instruction exception. */ - cpu_abort(env, "Unimplemented cp15 register read (c%d, c%d, {%d, %d})\n", - (insn >> 16) & 0xf, crm, op1, op2); - return 0; -} - void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val) { if ((env->uncached_cpsr & CPSR_M) == mode) { diff --git a/target-arm/helper.h b/target-arm/helper.h index a0034ae..21e9cfe 100644 --- a/target-arm/helper.h +++ b/target-arm/helper.h @@ -59,9 +59,6 @@ DEF_HELPER_0(cpsr_read, i32) DEF_HELPER_3(v7m_msr, void, env, i32, i32) DEF_HELPER_2(v7m_mrs, i32, env, i32) -DEF_HELPER_3(set_cp15, void, env, i32, i32) -DEF_HELPER_2(get_cp15, i32, env, i32) - DEF_HELPER_3(set_cp_reg, void, env, ptr, i32) DEF_HELPER_2(get_cp_reg, i32, env, ptr) DEF_HELPER_3(set_cp_reg64, void, env, ptr, i64) diff --git a/target-arm/translate.c b/target-arm/translate.c index 09e2165..ea5a1a6 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -2439,55 +2439,6 @@ static int disas_dsp_insn(CPUARMState *env, DisasContext *s, uint32_t insn) return 1; } -/* Disassemble system coprocessor (cp15) instruction. Return nonzero if - instruction is not defined. */ -static int disas_cp15_insn(CPUARMState *env, DisasContext *s, uint32_t insn) -{ - uint32_t rd; - TCGv tmp, tmp2; - - /* M profile cores use memory mapped registers instead of cp15. */ - if (arm_feature(env, ARM_FEATURE_M)) - return 1; - - if ((insn & (1 << 25)) == 0) { - return 1; - } - if ((insn & (1 << 4)) == 0) { - /* cdp */ - return 1; - } - - if (IS_USER(s)) { - return 1; - } - - rd = (insn >> 12) & 0xf; - - tmp2 = tcg_const_i32(insn); - if (insn & ARM_CP_RW_BIT) { - tmp = tcg_temp_new_i32(); - gen_helper_get_cp15(tmp, cpu_env, tmp2); - /* If the destination register is r15 then sets condition codes. */ - if (rd != 15) - store_reg(s, rd, tmp); - else - tcg_temp_free_i32(tmp); - } else { - tmp = load_reg(s, rd); - gen_helper_set_cp15(cpu_env, tmp2, tmp); - tcg_temp_free_i32(tmp); - /* Normally we would always end the TB here, but Linux - * arch/arm/mach-pxa/sleep.S expects two instructions following - * an MMU enable to execute from cache. Imitate this behaviour. */ - if (!arm_feature(env, ARM_FEATURE_XSCALE) || - (insn & 0x0fff0fff) != 0x0e010f10) - gen_lookup_tb(s); - } - tcg_temp_free_i32(tmp2); - return 0; -} - #define VFP_REG_SHR(x, n) (((n) > 0) ? (x) >> (n) : (x) << -(n)) #define VFP_SREG(insn, bigbit, smallbit) \ ((VFP_REG_SHR(insn, bigbit - 1) & 0x1e) | (((insn) >> (smallbit)) & 1)) @@ -6387,15 +6338,7 @@ static int disas_coproc_insn(CPUARMState * env, DisasContext *s, uint32_t insn) return 0; } - /* Fallback code: handle coprocessor registers not yet converted - * to ARMCPRegInfo. - */ - switch (cpnum) { - case 15: - return disas_cp15_insn (env, s, insn); - default: - return 1; - } + return 1; }