From patchwork Sun Apr 15 13:46:23 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 7859 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 9C5ED23E47 for ; Sun, 15 Apr 2012 13:46:57 +0000 (UTC) Received: from mail-iy0-f180.google.com (mail-iy0-f180.google.com [209.85.210.180]) by fiordland.canonical.com (Postfix) with ESMTP id 650F7A181A5 for ; Sun, 15 Apr 2012 13:46:57 +0000 (UTC) Received: by mail-iy0-f180.google.com with SMTP id e36so8543085iag.11 for ; Sun, 15 Apr 2012 06:46:57 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=X/7i3LB3FQCbRbBaHtVh0VAlAOGFarZQx0FPIKfda8k=; b=FakC7R5dqoEsp0kAxrpT8FJRBFXCN2kGMEafNDtgVBKGeUs9YdJaY8ZiQ7yt0fes2s 7QUbngRTfqYNa1xUOqA3BZMaiajpKovxfoghnq/c9vol6zkWJhmG9P7uhfklKWIdy1/q SfIa9ratr2wPK60Ao6z6oZdPBv2ZhWL3w+TRvO7uaBmWXYQWmMLk8K6ROvJX0mltV2yS QHKnms+P9CrKKvs35Qvv/axh7m4iuF95YQWWkGIaurcwk+DyWiqLP8glSbLplZcVeX+l Id13Gz6AFRUql0Y/DTQCXfIcOWIpQoEL5kGX6hywLhyikBTOj9d7pIs8CT5/1uu8gXJl btNg== Received: by 10.50.202.38 with SMTP id kf6mr3064247igc.30.1334497617203; Sun, 15 Apr 2012 06:46:57 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.70.69 with SMTP id c5csp22268ibj; Sun, 15 Apr 2012 06:46:56 -0700 (PDT) Received: by 10.180.101.136 with SMTP id fg8mr10888556wib.4.1334497615590; Sun, 15 Apr 2012 06:46:55 -0700 (PDT) Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk. [81.2.115.146]) by mx.google.com with ESMTPS id v6si15291845weq.146.2012.04.15.06.46.54 (version=TLSv1/SSLv3 cipher=OTHER); Sun, 15 Apr 2012 06:46:55 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) client-ip=81.2.115.146; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1SJPmd-0000FT-VG; Sun, 15 Apr 2012 14:46:27 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, =?UTF-8?q?Andreas=20F=C3=A4rber?= , Paul Brook Subject: [PATCH 30/32] target-arm: Move block cache ops to new cp15 framework Date: Sun, 15 Apr 2012 14:46:23 +0100 Message-Id: <1334497585-867-31-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1334497585-867-1-git-send-email-peter.maydell@linaro.org> References: <1334497585-867-1-git-send-email-peter.maydell@linaro.org> X-Gm-Message-State: ALoCoQljvsxkvV9D59Y1OqHxioX5XFmDfmQRHq9/BIVASNvSqG4/XQm17FT881aFaXpjsOCPlS2H Move the v6 optional block cache ops to the new cp15 framework. This includes only providing them on the CPUs which implemented them, rather than the previous blunderbuss approach of making all MCRR instructions on all CPUs act as NOPs. Signed-off-by: Peter Maydell --- target-arm/helper.c | 13 +++++++++++++ target-arm/translate.c | 7 +------ 2 files changed, 14 insertions(+), 6 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index ef99d1c..aef2e26 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -815,6 +815,19 @@ static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = { /* We never have a a block transfer operation in progress */ { .name = "BXSR", .cp = 15, .crn = 7, .crm = 12, .opc1 = 0, .opc2 = 4, .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 }, + /* The cache ops themselves: these all NOP for QEMU */ + { .name = "IICR", .cp = 15, .crm = 5, .opc1 = 0, + .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, + { .name = "IDCR", .cp = 15, .crm = 6, .opc1 = 0, + .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, + { .name = "CDCR", .cp = 15, .crm = 12, .opc1 = 0, + .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, + { .name = "PIR", .cp = 15, .crm = 12, .opc1 = 1, + .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, + { .name = "PDR", .cp = 15, .crm = 12, .opc1 = 2, + .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, + { .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0, + .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT }, REGINFO_SENTINEL }; diff --git a/target-arm/translate.c b/target-arm/translate.c index 6f7932f..09e2165 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -2451,12 +2451,7 @@ static int disas_cp15_insn(CPUARMState *env, DisasContext *s, uint32_t insn) return 1; if ((insn & (1 << 25)) == 0) { - if (insn & (1 << 20)) { - /* mrrc */ - return 1; - } - /* mcrr. Used for block cache operations, so implement as no-op. */ - return 0; + return 1; } if ((insn & (1 << 4)) == 0) { /* cdp */