From patchwork Sun Apr 15 13:46:21 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 7858 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id B2F3723E47 for ; Sun, 15 Apr 2012 13:46:56 +0000 (UTC) Received: from mail-iy0-f180.google.com (mail-iy0-f180.google.com [209.85.210.180]) by fiordland.canonical.com (Postfix) with ESMTP id 76F88A181A5 for ; Sun, 15 Apr 2012 13:46:56 +0000 (UTC) Received: by mail-iy0-f180.google.com with SMTP id e36so8543068iag.11 for ; Sun, 15 Apr 2012 06:46:56 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=clrNdIQJdFOxkbKvYO1I7eH28yDTZIXQq1E/xGKBSx0=; b=lGYV1rnTCHr2yxC4MvQCcUs4oXvSO/jnYzj67mnlMtbZDKwFnZIcQNo2VjX95Vsikn qlP1KhTGBeLENmFZ7io5uriOnjk+OCdnMekqG0h8HyCuw15FgJPnHEAcwQrY2q7aN1fu j6ungqd5ze4yGtNsZR2g/XyNzK+EZmvODWZUUAzQcAIY1L8MHjwstFTlf0Bd4UrBNydm h5qkCgMH/jsnMjxadmj4tbLhiT5iCP2KHgRYnVCB8tLG3dqqLFs8BWqbfEXJTVJGWhBe oyMSyaNrB8kEjw+1xyomPDBQGUs5p6ldJyhJ2vvizaJaz2sj5VvHeIfxHwFg+XseKHvw csSg== Received: by 10.50.149.163 with SMTP id ub3mr3067277igb.30.1334497616266; Sun, 15 Apr 2012 06:46:56 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.70.69 with SMTP id c5csp22266ibj; Sun, 15 Apr 2012 06:46:55 -0700 (PDT) Received: by 10.180.79.72 with SMTP id h8mr10990295wix.1.1334497614432; Sun, 15 Apr 2012 06:46:54 -0700 (PDT) Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk. [81.2.115.146]) by mx.google.com with ESMTPS id bt8si4812574wib.40.2012.04.15.06.46.53 (version=TLSv1/SSLv3 cipher=OTHER); Sun, 15 Apr 2012 06:46:54 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) client-ip=81.2.115.146; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1SJPmd-0000FP-RV; Sun, 15 Apr 2012 14:46:27 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, =?UTF-8?q?Andreas=20F=C3=A4rber?= , Paul Brook Subject: [PATCH 28/32] target-arm: Convert final ID registers Date: Sun, 15 Apr 2012 14:46:21 +0100 Message-Id: <1334497585-867-29-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1334497585-867-1-git-send-email-peter.maydell@linaro.org> References: <1334497585-867-1-git-send-email-peter.maydell@linaro.org> X-Gm-Message-State: ALoCoQmalwKdhxImEjq60or1GZS95xf26Y0UwYw0xILTmwAnHwI/1SMdbQAXpv6TfCSPDH1DUJXX Convert the final ID registers to the new cp15 scheme. Signed-off-by: Peter Maydell --- target-arm/cpu.c | 2 - target-arm/helper.c | 111 +++++++++++++++++++++++++++++---------------------- 2 files changed, 63 insertions(+), 50 deletions(-) diff --git a/target-arm/cpu.c b/target-arm/cpu.c index 52ee2a9..dc124f6 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -72,11 +72,9 @@ static void arm_cpu_reset(CPUState *s) memset(env, 0, offsetof(CPUARMState, breakpoints)); g_hash_table_foreach(env->cp_regs, cp_reg_reset, env); - env->cp15.c0_cpuid = cpu->midr; env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid; env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0; env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1; - env->cp15.c0_cachetype = cpu->ctr; if (arm_feature(env, ARM_FEATURE_IWMMXT)) { env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q'; diff --git a/target-arm/helper.c b/target-arm/helper.c index 2b65024..ef99d1c 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -1007,6 +1007,69 @@ void register_cp_regs_for_features(ARMCPU *cpu) if (arm_feature(env, ARM_FEATURE_MPIDR)) { define_arm_cp_regs(env, mpidr_cp_reginfo); } + /* Slightly awkwardly, the OMAP and StrongARM cores need all of + * cp15 crn=0 to be writes-ignored. + */ + { + ARMCPRegInfo id_cp_reginfo[] = { + /* Note that the MIDR isn't a simple constant register because + * of the TI925 behaviour where writes to another register can + * cause the MIDR value to change. + */ + { .name = "MIDR", + .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0, + .access = PL1_R, .resetvalue = cpu->midr, + .writefn = arm_cp_write_ignore, + .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid) }, + { .name = "CTR", + .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 1, + .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->ctr }, + { .name = "TCMTR", + .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 2, + .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, + { .name = "TLBTR", + .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 3, + .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, + /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */ + { .name = "DUMMY", + .cp = 15, .crn = 0, .crm = 3, .opc1 = 0, .opc2 = CP_ANY, + .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, + { .name = "DUMMY", + .cp = 15, .crn = 0, .crm = 4, .opc1 = 0, .opc2 = CP_ANY, + .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, + { .name = "DUMMY", + .cp = 15, .crn = 0, .crm = 5, .opc1 = 0, .opc2 = CP_ANY, + .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, + { .name = "DUMMY", + .cp = 15, .crn = 0, .crm = 6, .opc1 = 0, .opc2 = CP_ANY, + .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, + { .name = "DUMMY", + .cp = 15, .crn = 0, .crm = 7, .opc1 = 0, .opc2 = CP_ANY, + .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, + REGINFO_SENTINEL + }; + ARMCPRegInfo crn0_wi_reginfo = { + .name = "CRN0_WI", .cp = 15, .crn = 0, .crm = CP_ANY, + .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_W, .type = ARM_CP_NOP + }; + if (arm_feature(env, ARM_FEATURE_OMAPCP) || + arm_feature(env, ARM_FEATURE_STRONGARM)) { + ARMCPRegInfo *r; + /* Register the blanket "writes ignored" value first, then fix + * up the specific ID registers to allow write access and register + * those; they will override the "writes ignored" wildcard. + */ + define_one_arm_cp_reg(env, &crn0_wi_reginfo); + for (r = id_cp_reginfo; r->type != ARM_CP_SENTINEL; r++) { + r->access = PL1_RW; + define_one_arm_cp_reg(env, r); + } + } else { + /* Just register the standard ID registers */ + define_arm_cp_regs(env, id_cp_reginfo); + } + } + if (arm_feature(env, ARM_FEATURE_AUXCR)) { ARMCPRegInfo auxcr = { .name = "AUXCR", .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1, @@ -2091,21 +2154,6 @@ void HELPER(set_cp15)(CPUARMState *env, uint32_t insn, uint32_t val) op1 = (insn >> 21) & 7; op2 = (insn >> 5) & 7; crm = insn & 0xf; - switch ((insn >> 16) & 0xf) { - case 0: - /* ID codes. */ - if (arm_feature(env, ARM_FEATURE_XSCALE)) - break; - if (arm_feature(env, ARM_FEATURE_OMAPCP)) - break; - goto bad_reg; - case 4: /* Reserved. */ - goto bad_reg; - case 12: /* Reserved. */ - goto bad_reg; - } - return; -bad_reg: /* ??? For debugging only. Should raise illegal instruction exception. */ cpu_abort(env, "Unimplemented cp15 register write (c%d, c%d, {%d, %d})\n", (insn >> 16) & 0xf, crm, op1, op2); @@ -2120,39 +2168,6 @@ uint32_t HELPER(get_cp15)(CPUARMState *env, uint32_t insn) op1 = (insn >> 21) & 7; op2 = (insn >> 5) & 7; crm = insn & 0xf; - switch ((insn >> 16) & 0xf) { - case 0: /* ID codes. */ - switch (op1) { - case 0: - switch (crm) { - case 0: - switch (op2) { - case 0: /* Device ID. */ - return env->cp15.c0_cpuid; - case 1: /* Cache Type. */ - return env->cp15.c0_cachetype; - case 2: /* TCM status. */ - return 0; - case 3: /* TLB type register. */ - return 0; /* No lockable TLB entries. */ - default: - goto bad_reg; - } - case 3: case 4: case 5: case 6: case 7: - return 0; - default: - goto bad_reg; - } - default: - goto bad_reg; - } - case 4: /* Reserved. */ - goto bad_reg; - case 11: /* TCM DMA control. */ - case 12: /* Reserved. */ - goto bad_reg; - } -bad_reg: /* ??? For debugging only. Should raise illegal instruction exception. */ cpu_abort(env, "Unimplemented cp15 register read (c%d, c%d, {%d, %d})\n", (insn >> 16) & 0xf, crm, op1, op2);