From patchwork Sun Apr 15 13:46:13 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 7849 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 221BC23E47 for ; Sun, 15 Apr 2012 13:46:46 +0000 (UTC) Received: from mail-iy0-f180.google.com (mail-iy0-f180.google.com [209.85.210.180]) by fiordland.canonical.com (Postfix) with ESMTP id DF0D9A181B4 for ; Sun, 15 Apr 2012 13:46:45 +0000 (UTC) Received: by mail-iy0-f180.google.com with SMTP id e36so8543085iag.11 for ; Sun, 15 Apr 2012 06:46:45 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=uk5oRGyGmYiueoCFcSpchzMfA/8VoK/9/3tovWtZvhM=; b=kc/csWYZ7EAUJvpVGViwl56uaSe2bQBeN7x5PtT0hHG4HVFy9sIYDUNbwTzjbj5d48 MEzJDJ8w74+2hBuQjYB0NAY2QwXv3VTG5MR1tj4QhF5GJrWf/Fox1F7EliHHoW1nW2x5 9b0y55uk0AJnnxkE1MwcOcGZCYNnq8mGrb+hQLtRPGz6DSEbDFRuSAcApqdzqpCaIVZM z7OaEw456BjgaLXbNUJlc3geFoQLP2nig2M9Ivk7swRSF7X6+6CSQC5AU4v1uLbSWjGv yEIGtRjWpC+60+oTpfppF28AUXj4ILecFCOcjIRNgX+KssxTXV2/z89J0Y1lZUmOCRLd 15EA== Received: by 10.50.187.226 with SMTP id fv2mr3152573igc.40.1334497605694; Sun, 15 Apr 2012 06:46:45 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.70.69 with SMTP id c5csp22234ibj; Sun, 15 Apr 2012 06:46:45 -0700 (PDT) Received: by 10.180.80.70 with SMTP id p6mr1523364wix.21.1334497604040; Sun, 15 Apr 2012 06:46:44 -0700 (PDT) Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk. [81.2.115.146]) by mx.google.com with ESMTPS id s65si15332441weq.63.2012.04.15.06.46.43 (version=TLSv1/SSLv3 cipher=OTHER); Sun, 15 Apr 2012 06:46:44 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) client-ip=81.2.115.146; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1SJPmd-0000F9-8t; Sun, 15 Apr 2012 14:46:27 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, =?UTF-8?q?Andreas=20F=C3=A4rber?= , Paul Brook Subject: [PATCH 20/32] target-arm: Convert cp15 VA-PA translation registers Date: Sun, 15 Apr 2012 14:46:13 +0100 Message-Id: <1334497585-867-21-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1334497585-867-1-git-send-email-peter.maydell@linaro.org> References: <1334497585-867-1-git-send-email-peter.maydell@linaro.org> X-Gm-Message-State: ALoCoQkVueilVDVJFcUsDVPDAkVrjprak7o8c2VtGDk4uuZIkKrcoz6wlsuXEaypQmvJXpRclo64 Convert the cp15 VA-PA translation registers (a subset of the crn=7 regs) to the new scheme. Signed-off-by: Peter Maydell --- target-arm/helper.c | 108 ++++++++++++++++++++++++++++++-------------------- 1 files changed, 65 insertions(+), 43 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index 32fa49a..58923db 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -4,6 +4,13 @@ #include "host-utils.h" #include "sysemu.h" +#ifndef CONFIG_USER_ONLY +static inline int get_phys_addr(CPUARMState *env, uint32_t address, + int access_type, int is_user, + uint32_t *phys_ptr, int *prot, + target_ulong *page_size); +#endif + void cpu_state_reset(CPUARMState *env) { cpu_reset(ENV_GET_CPU(env)); @@ -422,6 +429,61 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = { REGINFO_SENTINEL }; +static int par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) +{ + if (arm_feature(env, ARM_FEATURE_V7)) { + env->cp15.c7_par = value & 0xfffff6ff; + } else { + env->cp15.c7_par = value & 0xfffff1ff; + } + return 0; +} + +#ifndef CONFIG_USER_ONLY +/* get_phys_addr() isn't present for user-mode-only targets */ +static int ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) +{ + uint32_t phys_addr; + target_ulong page_size; + int prot; + int ret, is_user = ri->opc2 & 2; + int access_type = ri->opc2 & 1; + + if (ri->opc2 & 4) { + /* Other states are only available with TrustZone */ + return EXCP_UDEF; + } + ret = get_phys_addr(env, value, access_type, is_user, + &phys_addr, &prot, &page_size); + if (ret == 0) { + /* We do not set any attribute bits in the PAR */ + if (page_size == (1 << 24) + && arm_feature(env, ARM_FEATURE_V7)) { + env->cp15.c7_par = (phys_addr & 0xff000000) | 1 << 1; + } else { + env->cp15.c7_par = phys_addr & 0xfffff000; + } + } else { + env->cp15.c7_par = ((ret & (10 << 1)) >> 5) | + ((ret & (12 << 1)) >> 6) | + ((ret & 0xf) << 1) | 1; + } + return 0; +} +#endif + +static const ARMCPRegInfo vapa_cp_reginfo[] = { + { .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0, + .access = PL1_RW, .resetvalue = 0, + .fieldoffset = offsetof(CPUARMState, cp15.c7_par), + .writefn = par_write }, +#ifndef CONFIG_USER_ONLY + { .name = "ATS", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = CP_ANY, + .access = PL1_W, .writefn = ats_write }, +#endif + REGINFO_SENTINEL +}; + /* Return basic MPU access permission bits. */ static uint32_t simple_mpu_ap_bits(uint32_t val) { @@ -679,6 +741,9 @@ void register_cp_regs_for_features(ARMCPU *cpu) if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) { define_arm_cp_regs(env, generic_timer_cp_reginfo); } + if (arm_feature(env, ARM_FEATURE_VAPA)) { + define_arm_cp_regs(env, vapa_cp_reginfo); + } if (arm_feature(env, ARM_FEATURE_OMAPCP)) { define_arm_cp_regs(env, omap_cp_reginfo); } @@ -1825,46 +1890,6 @@ void HELPER(set_cp15)(CPUARMState *env, uint32_t insn, uint32_t val) if (op1 != 0) { goto bad_reg; } - /* No cache, so nothing to do except VA->PA translations. */ - if (arm_feature(env, ARM_FEATURE_VAPA)) { - switch (crm) { - case 4: - if (arm_feature(env, ARM_FEATURE_V7)) { - env->cp15.c7_par = val & 0xfffff6ff; - } else { - env->cp15.c7_par = val & 0xfffff1ff; - } - break; - case 8: { - uint32_t phys_addr; - target_ulong page_size; - int prot; - int ret, is_user = op2 & 2; - int access_type = op2 & 1; - - if (op2 & 4) { - /* Other states are only available with TrustZone */ - goto bad_reg; - } - ret = get_phys_addr(env, val, access_type, is_user, - &phys_addr, &prot, &page_size); - if (ret == 0) { - /* We do not set any attribute bits in the PAR */ - if (page_size == (1 << 24) - && arm_feature(env, ARM_FEATURE_V7)) { - env->cp15.c7_par = (phys_addr & 0xff000000) | 1 << 1; - } else { - env->cp15.c7_par = phys_addr & 0xfffff000; - } - } else { - env->cp15.c7_par = ((ret & (10 << 1)) >> 5) | - ((ret & (12 << 1)) >> 6) | - ((ret & 0xf) << 1) | 1; - } - break; - } - } - } break; case 9: if (arm_feature(env, ARM_FEATURE_OMAPCP)) @@ -2072,9 +2097,6 @@ uint32_t HELPER(get_cp15)(CPUARMState *env, uint32_t insn) } } case 7: /* Cache control. */ - if (crm == 4 && op1 == 0 && op2 == 0) { - return env->cp15.c7_par; - } /* FIXME: Should only clear Z flag if destination is r15. */ env->ZF = 0; return 0;