From patchwork Sun Apr 15 13:46:08 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 7853 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 9E81D23E47 for ; Sun, 15 Apr 2012 13:46:51 +0000 (UTC) Received: from mail-iy0-f180.google.com (mail-iy0-f180.google.com [209.85.210.180]) by fiordland.canonical.com (Postfix) with ESMTP id 67585A181A5 for ; Sun, 15 Apr 2012 13:46:51 +0000 (UTC) Received: by mail-iy0-f180.google.com with SMTP id e36so8543085iag.11 for ; Sun, 15 Apr 2012 06:46:51 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=rEWXB/n7UPpyRcw6lNPIBMFDaBFNi1wik0GI33VDrTo=; b=Npy3wZrwwWvjgKMylNDIRBCapfECJJGiV7xNcpySQmrFudoeMxJDxlD/Rel/TpqJSI vPAmdZPZYGVEUwZL9/YP7YwqMlIiWZjDQoRa3xms7rTghaJxqGjeOxTYrYbuqh4zwDPz q4mo4/cTMYNh5kFoTMhzIMj1j2zpkKe4zy3mRe6hi5/sNanC8ftJiYZILbfeZUX1cD8g PneeI60yKBRAm5elcmOTr/4aEjCCtBxO/NPo/lOJ06B9hhsVeIl6gW0dv6IZWzqzsHH0 FcRAm3QLR3Vcpv8mVZVdlhjbtKSjDzNXMtS/gNxNc3uBSOo48nh4C55izL3lD93aRfUG KQNw== Received: by 10.50.242.5 with SMTP id wm5mr3138660igc.40.1334497611212; Sun, 15 Apr 2012 06:46:51 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.70.69 with SMTP id c5csp22248ibj; Sun, 15 Apr 2012 06:46:50 -0700 (PDT) Received: by 10.180.80.104 with SMTP id q8mr10809728wix.14.1334497610175; Sun, 15 Apr 2012 06:46:50 -0700 (PDT) Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk. [81.2.115.146]) by mx.google.com with ESMTPS id q19si15357945wec.9.2012.04.15.06.46.49 (version=TLSv1/SSLv3 cipher=OTHER); Sun, 15 Apr 2012 06:46:50 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) client-ip=81.2.115.146; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 81.2.115.146 as permitted sender) smtp.mail=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.72) (envelope-from ) id 1SJPmc-0000Ez-TQ; Sun, 15 Apr 2012 14:46:26 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, =?UTF-8?q?Andreas=20F=C3=A4rber?= , Paul Brook Subject: [PATCH 15/32] target-arm: Convert cp15 crn=2 registers Date: Sun, 15 Apr 2012 14:46:08 +0100 Message-Id: <1334497585-867-16-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: <1334497585-867-1-git-send-email-peter.maydell@linaro.org> References: <1334497585-867-1-git-send-email-peter.maydell@linaro.org> X-Gm-Message-State: ALoCoQkOzidt/ZOCAEY8OV/zXm06bxIvf9Jnm62jCaQSz6zDnEql+5tuCDqNZk5xoJbafsJDn1CN Convert the cp15 crn=2 registers (MMU page table control, MPU cache control) to the new scheme. Signed-off-by: Peter Maydell --- target-arm/cpu.c | 1 - target-arm/helper.c | 88 +++++++++++++++++++-------------------------------- 2 files changed, 33 insertions(+), 56 deletions(-) diff --git a/target-arm/cpu.c b/target-arm/cpu.c index 43f252f..083da3e 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -131,7 +131,6 @@ static void arm_cpu_reset(CPUState *s) } } env->vfp.xregs[ARM_VFP_FPEXC] = 0; - env->cp15.c2_base_mask = 0xffffc000u; #endif set_flush_to_zero(1, &env->vfp.standard_fp_status); set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status); diff --git a/target-arm/helper.c b/target-arm/helper.c index 7343c2a..19e27c3 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -416,9 +416,32 @@ static const ARMCPRegInfo pmsav5_cp_reginfo[] = { { .name = "INSN_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 3, .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c5_insn), .resetvalue = 0, }, + { .name = "DCACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0, + .access = PL1_RW, + .fieldoffset = offsetof(CPUARMState, cp15.c2_data), .resetvalue = 0, }, + { .name = "ICACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1, + .access = PL1_RW, + .fieldoffset = offsetof(CPUARMState, cp15.c2_insn), .resetvalue = 0, }, REGINFO_SENTINEL }; +static int vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + value &= 7; + env->cp15.c2_control = value; + env->cp15.c2_mask = ~(((uint32_t)0xffffffffu) >> value); + env->cp15.c2_base_mask = ~((uint32_t)0x3fffu >> value); + return 0; +} + +static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri) +{ + env->cp15.c2_base_mask = 0xffffc000u; + env->cp15.c2_control = 0; + env->cp15.c2_mask = 0; +} + static const ARMCPRegInfo vmsa_cp_reginfo[] = { { .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0, .access = PL1_RW, @@ -426,6 +449,16 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = { { .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c5_insn), .resetvalue = 0, }, + { .name = "TTBR0", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0, + .access = PL1_RW, + .fieldoffset = offsetof(CPUARMState, cp15.c2_base0), .resetvalue = 0, }, + { .name = "TTBR1", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1, + .access = PL1_RW, + .fieldoffset = offsetof(CPUARMState, cp15.c2_base0), .resetvalue = 0, }, + { .name = "TTBCR", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2, + .access = PL1_RW, .writefn = vmsa_ttbcr_write, + .resetfn = vmsa_ttbcr_reset, + .fieldoffset = offsetof(CPUARMState, cp15.c2_control) }, REGINFO_SENTINEL }; @@ -1597,37 +1630,6 @@ void HELPER(set_cp15)(CPUARMState *env, uint32_t insn, uint32_t val) goto bad_reg; } break; - case 2: /* MMU Page table control / MPU cache control. */ - if (arm_feature(env, ARM_FEATURE_MPU)) { - switch (op2) { - case 0: - env->cp15.c2_data = val; - break; - case 1: - env->cp15.c2_insn = val; - break; - default: - goto bad_reg; - } - } else { - switch (op2) { - case 0: - env->cp15.c2_base0 = val; - break; - case 1: - env->cp15.c2_base1 = val; - break; - case 2: - val &= 7; - env->cp15.c2_control = val; - env->cp15.c2_mask = ~(((uint32_t)0xffffffffu) >> val); - env->cp15.c2_base_mask = ~((uint32_t)0x3fffu >> val); - break; - default: - goto bad_reg; - } - } - break; case 4: /* Reserved. */ goto bad_reg; case 6: /* MMU Fault address / MPU base/size. */ @@ -1963,30 +1965,6 @@ uint32_t HELPER(get_cp15)(CPUARMState *env, uint32_t insn) default: goto bad_reg; } - case 2: /* MMU Page table control / MPU cache control. */ - if (arm_feature(env, ARM_FEATURE_MPU)) { - switch (op2) { - case 0: - return env->cp15.c2_data; - break; - case 1: - return env->cp15.c2_insn; - break; - default: - goto bad_reg; - } - } else { - switch (op2) { - case 0: - return env->cp15.c2_base0; - case 1: - return env->cp15.c2_base1; - case 2: - return env->cp15.c2_control; - default: - goto bad_reg; - } - } case 4: /* Reserved. */ goto bad_reg; case 6: /* MMU Fault address. */